From 2861e8d7f4d2c25c712805446ccf603d77e4b935 Mon Sep 17 00:00:00 2001
From: Grygorii Strashko <grygorii.strashko@ti.com>
Date: Mon, 13 Sep 2021 18:19:53 +0300
Subject: [PATCH] net: ethernet: ti: icssg_prueth: move miig_rt api in separate
 file

No need to have those functions as inline and as preparation for adding
"mii" support.

Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
 drivers/net/ethernet/ti/Makefile        |  2 +-
 drivers/net/ethernet/ti/icss_mii_rt.h   | 82 ++---------------------
 drivers/net/ethernet/ti/icssg_mii_cfg.c | 89 +++++++++++++++++++++++++
 3 files changed, 96 insertions(+), 77 deletions(-)
 create mode 100644 drivers/net/ethernet/ti/icssg_mii_cfg.c

diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile
index 5f99e7b48103..b40292eff9bf 100644
--- a/drivers/net/ethernet/ti/Makefile
+++ b/drivers/net/ethernet/ti/Makefile
@@ -31,4 +31,4 @@ obj-$(CONFIG_TI_K3_AM65_CPTS) += am65-cpts.o
 obj-$(CONFIG_TI_ICSS_IEP) += icss_iep.o
 
 obj-$(CONFIG_TI_ICSSG_PRUETH) += icssg-prueth.o
-icssg-prueth-y := icssg_prueth.o icssg_classifier.o icssg_ethtool.o icssg_queues.o icssg_config.o k3-cppi-desc-pool.o
+icssg-prueth-y := icssg_prueth.o icssg_classifier.o icssg_ethtool.o icssg_queues.o icssg_config.o k3-cppi-desc-pool.o icssg_mii_cfg.o
diff --git a/drivers/net/ethernet/ti/icss_mii_rt.h b/drivers/net/ethernet/ti/icss_mii_rt.h
index 836060ffdd4a..88b3c9cf222f 100644
--- a/drivers/net/ethernet/ti/icss_mii_rt.h
+++ b/drivers/net/ethernet/ti/icss_mii_rt.h
@@ -123,81 +123,11 @@ enum mii_mode { MII_MODE_MII = 0, MII_MODE_RGMII, MII_MODE_SGMII };
 #define RGMII_CFG_SPEED_100M	1
 #define RGMII_CFG_SPEED_1G	2
 
-static inline void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg)
-{
-	u32 val;
-
-	if (mii == ICSS_MII0) {
-		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg);
-	} else {
-	/* Errata workaround: IEP1 is not read by h/w unless IEP0 is written */
-		regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val);
-		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg);
-		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val);
-	}
-}
-
-static inline void icssg_update_rgmii_cfg(struct regmap *miig_rt, int speed,
-					  int duplex, int mii)
-{
-	u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0;
-	u32 inband_en_mask, inband_val = 0;
-
-	gig_en_mask = (mii == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 :
-					RGMII_CFG_GIG_EN_MII1;
-	if (speed == SPEED_1000)
-		gig_val = gig_en_mask;
-	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val);
-
-	inband_en_mask = (mii == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 :
-					RGMII_CFG_INBAND_EN_MII1;
-	if (speed == SPEED_10)
-		inband_val = inband_en_mask;
-	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val);
-
-	full_duplex_mask = (mii == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 :
-					   RGMII_CFG_FULL_DUPLEX_MII1;
-	if (duplex == DUPLEX_FULL)
-		full_duplex_val = full_duplex_mask;
-	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask,
-			   full_duplex_val);
-}
-
-static inline u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt,
-					       u32 mask, u32 shift)
-{
-	u32 val;
-
-	regmap_read(miig_rt, RGMII_CFG_OFFSET, &val);
-	val &= mask;
-	val >>= shift;
-
-	return val;
-}
-
-static inline u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii)
-{
-	u32 shift = RGMII_CFG_SPEED_MII0_SHIFT, mask = RGMII_CFG_SPEED_MII0;
-
-	if (mii == ICSS_MII1) {
-		shift = RGMII_CFG_SPEED_MII1_SHIFT;
-		mask = RGMII_CFG_SPEED_MII1;
-	}
-
-	return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift);
-}
-
-static inline u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii)
-{
-	u32 shift = RGMII_CFG_FULLDUPLEX_MII0_SHIFT;
-	u32 mask = RGMII_CFG_FULLDUPLEX_MII0;
-
-	if (mii == ICSS_MII1) {
-		shift = RGMII_CFG_FULLDUPLEX_MII1_SHIFT;
-		mask = RGMII_CFG_FULLDUPLEX_MII1;
-	}
-
-	return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift);
-}
+void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg);
+void icssg_update_rgmii_cfg(struct regmap *miig_rt, int speed,
+			    int duplex, int mii);
+u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift);
+u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii);
+u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii);
 
 #endif /* __NET_PRUSS_MII_RT_H__ */
diff --git a/drivers/net/ethernet/ti/icssg_mii_cfg.c b/drivers/net/ethernet/ti/icssg_mii_cfg.c
new file mode 100644
index 000000000000..eea04806ad28
--- /dev/null
+++ b/drivers/net/ethernet/ti/icssg_mii_cfg.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Texas Instruments ICSSG Ethernet Driver
+ *
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include <linux/etherdevice.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include "icss_mii_rt.h"
+#include "icssg_prueth.h"
+
+void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg)
+{
+	u32 val;
+
+	if (mii == ICSS_MII0) {
+		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg);
+	} else {
+	/* Errata workaround: IEP1 is not read by h/w unless IEP0 is written */
+		regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val);
+		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg);
+		regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val);
+	}
+}
+
+void icssg_update_rgmii_cfg(struct regmap *miig_rt, int speed,
+			    int duplex, int mii)
+{
+	u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0;
+	u32 inband_en_mask, inband_val = 0;
+
+	gig_en_mask = (mii == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 :
+					RGMII_CFG_GIG_EN_MII1;
+	if (speed == SPEED_1000)
+		gig_val = gig_en_mask;
+	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val);
+
+	inband_en_mask = (mii == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 :
+					RGMII_CFG_INBAND_EN_MII1;
+	if (speed == SPEED_10)
+		inband_val = inband_en_mask;
+	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val);
+
+	full_duplex_mask = (mii == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 :
+					   RGMII_CFG_FULL_DUPLEX_MII1;
+	if (duplex == DUPLEX_FULL)
+		full_duplex_val = full_duplex_mask;
+	regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask,
+			   full_duplex_val);
+}
+
+u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift)
+{
+	u32 val;
+
+	regmap_read(miig_rt, RGMII_CFG_OFFSET, &val);
+	val &= mask;
+	val >>= shift;
+
+	return val;
+}
+
+u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii)
+{
+	u32 shift = RGMII_CFG_SPEED_MII0_SHIFT, mask = RGMII_CFG_SPEED_MII0;
+
+	if (mii == ICSS_MII1) {
+		shift = RGMII_CFG_SPEED_MII1_SHIFT;
+		mask = RGMII_CFG_SPEED_MII1;
+	}
+
+	return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift);
+}
+
+u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii)
+{
+	u32 shift = RGMII_CFG_FULLDUPLEX_MII0_SHIFT;
+	u32 mask = RGMII_CFG_FULLDUPLEX_MII0;
+
+	if (mii == ICSS_MII1) {
+		shift = RGMII_CFG_FULLDUPLEX_MII1_SHIFT;
+		mask = RGMII_CFG_FULLDUPLEX_MII1;
+	}
+
+	return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift);
+}
