wrk

MakeBuildrootEnv.sh

@@ -2,9 +2,9 @@
 PSGWRKDIR=`pwd`
 cd ..
 rm -rf buildroot
-git clone git://git.buildroot.net/buildroot
+git clone https://github.com/buildroot/buildroot.git
 cd buildroot
-git checkout 2021.11.3
+#git checkout 2021.11.3
 #==== Patches
 for i in ../PSG/patches/*.patch
 do
@@ -16,5 +16,5 @@ chmod a+x *.sh
 cp ../PSG/configs/* ./configs
 git add .
 git commit -m "PSG wrk changes and setup"
-make  BR2_EXTERNAL=../PSG iot2050_defconfig
+make  BR2_EXTERNAL=../PSG iot2050_V2_defconfig
 cd $PSGWRKDIR

board/PSG/iot2050/BUILD

@@ -1 +1 @@
-144
+IOT2050_V2_200

board/PSG/iot2050/files/0001-firmware-ti_sci-Add-support-for-getting-resource-wit.patch

@@ -1,221 +0,0 @@
-From dfbe48d84d617d5b2936a8f39e63ab786b077682 Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Thu, 6 Aug 2020 13:18:16 +0530
-Subject: [PATCH 01/26] firmware: ti_sci: Add support for getting resource with
- subtype
-
-With SYSFW ABI 3.0 changes, interrupts coming out of an interrupt
-controller is identified by a type and it is consistent across SoCs.
-Similarly global events for Interrupt aggregator. So add an API to get
-resource range using a resource type.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- drivers/firmware/ti_sci.c              | 105 ++++++++++++++++++++-----
- include/linux/soc/ti/ti_sci_protocol.h |  13 +++
- 2 files changed, 97 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
-index 825891f6e6cd..72d53423bd20 100644
---- a/drivers/firmware/ti_sci.c
-+++ b/drivers/firmware/ti_sci.c
-@@ -3410,10 +3410,29 @@ void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
- EXPORT_SYMBOL_GPL(ti_sci_release_resource);
- 
- /**
-- * devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device
-+ * ti_sci_get_num_resources() - Get the number of resources in TISCI resource
-+ * @res:	Pointer to the TISCI resource
-+ *
-+ * Return: Total number of available resources.
-+ */
-+u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
-+{
-+	u32 set, count = 0;
-+
-+	for (set = 0; set < res->sets; set++)
-+		count += res->desc[set].num;
-+
-+	return count;
-+}
-+EXPORT_SYMBOL_GPL(ti_sci_get_num_resources);
-+
-+/**
-+ * devm_ti_sci_get_resource_sets() - Get a TISCI resources assigned to a device
-  * @handle:	TISCI handle
-  * @dev:	Device pointer to which the resource is assigned
-- * @of_prop:	property name by which the resource are represented
-+ * @dev_id:	TISCI device id to which the resource is assigned
-+ * @sub_types:	Array of sub_types assigned corresponding to device
-+ * @sets:	Number of sub_types
-  *
-  * Note: This function expects of_prop to be in the form of tuples
-  *	<type, subtype>. Allocates and initializes ti_sci_resource structure
-@@ -3423,27 +3442,21 @@ EXPORT_SYMBOL_GPL(ti_sci_release_resource);
-  * Return: Pointer to ti_sci_resource if all went well else appropriate
-  *	   error pointer.
-  */
--struct ti_sci_resource *
--devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
--			    struct device *dev, u32 dev_id, char *of_prop)
-+static struct ti_sci_resource *
-+devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
-+			      struct device *dev, u32 dev_id, u32 *sub_types,
-+			      u32 sets)
- {
- 	u32 resource_subtype;
- 	u16 resource_type;
- 	struct ti_sci_resource *res;
- 	bool valid_set = false;
--	int sets, i, ret;
-+	int i, ret;
- 
- 	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
- 	if (!res)
- 		return ERR_PTR(-ENOMEM);
- 
--	sets = of_property_count_elems_of_size(dev_of_node(dev), of_prop,
--					       sizeof(u32));
--	if (sets < 0) {
--		dev_err(dev, "%s resource type ids not available\n", of_prop);
--		return ERR_PTR(sets);
--	}
--
- 	res->sets = sets;
- 
- 	res->desc = devm_kcalloc(dev, res->sets, sizeof(*res->desc),
-@@ -3459,18 +3472,13 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
- 	}
- 
- 	for (i = 0; i < res->sets; i++) {
--		ret = of_property_read_u32_index(dev_of_node(dev), of_prop, i,
--						 &resource_subtype);
--		if (ret)
--			return ERR_PTR(-EINVAL);
--
- 		ret = handle->ops.rm_core_ops.get_range(handle, dev_id,
--							resource_subtype,
-+							sub_types[i],
- 							&res->desc[i].start,
- 							&res->desc[i].num);
- 		if (ret) {
- 			dev_dbg(dev, "type %d subtype %d not allocated for host %d\n",
--				resource_type, resource_subtype,
-+				resource_type, sub_types[i],
- 				handle_to_ti_sci_info(handle)->host_id);
- 			res->desc[i].start = 0;
- 			res->desc[i].num = 0;
-@@ -3479,7 +3487,7 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
- 
- 		valid_set = true;
- 		dev_dbg(dev, "res type = %d, subtype = %d, start = %d, num = %d\n",
--			resource_type, resource_subtype, res->desc[i].start,
-+			resource_type, sub_types[i], res->desc[i].start,
- 			res->desc[i].num);
- 
- 		res->desc[i].res_map =
-@@ -3495,8 +3503,63 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
- 
- 	return ERR_PTR(-EINVAL);
- }
-+
-+/**
-+ * devm_ti_sci_get_of_resource() - Get a TISCI resource assigned to a device
-+ * @handle:	TISCI handle
-+ * @dev:	Device pointer to which the resource is assigned
-+ * @dev_id:	TISCI device id to which the resource is assigned
-+ * @of_prop:	property name by which the resource are represented
-+ *
-+ * Return: Pointer to ti_sci_resource if all went well else appropriate
-+ *	   error pointer.
-+ */
-+struct ti_sci_resource *
-+devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
-+			    struct device *dev, u32 dev_id, char *of_prop)
-+{
-+	struct ti_sci_resource *res;
-+	u32 *sub_types;
-+	int sets;
-+
-+	sets = of_property_count_elems_of_size(dev_of_node(dev), of_prop,
-+					       sizeof(u32));
-+	if (sets < 0) {
-+		dev_err(dev, "%s resource type ids not available\n", of_prop);
-+		return ERR_PTR(sets);
-+	}
-+
-+	sub_types = kcalloc(sets, sizeof(*sub_types), GFP_KERNEL);
-+	if (!sub_types)
-+		return ERR_PTR(-ENOMEM);
-+
-+	of_property_read_u32_array(dev_of_node(dev), of_prop, sub_types, sets);
-+	res = devm_ti_sci_get_resource_sets(handle, dev, dev_id, sub_types,
-+					    sets);
-+
-+	kfree(sub_types);
-+	return res;
-+}
- EXPORT_SYMBOL_GPL(devm_ti_sci_get_of_resource);
- 
-+/**
-+ * devm_ti_sci_get_resource() - Get a resource range assigned to the device
-+ * @handle:	TISCI handle
-+ * @dev:	Device pointer to which the resource is assigned
-+ * @dev_id:	TISCI device id to which the resource is assigned
-+ * @suub_type:	TISCI resource subytpe representing the resource.
-+ *
-+ * Return: Pointer to ti_sci_resource if all went well else appropriate
-+ *	   error pointer.
-+ */
-+struct ti_sci_resource *
-+devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
-+			 u32 dev_id, u32 sub_type)
-+{
-+	return devm_ti_sci_get_resource_sets(handle, dev, dev_id, &sub_type, 1);
-+}
-+EXPORT_SYMBOL_GPL(devm_ti_sci_get_resource);
-+
- static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode,
- 				void *cmd)
- {
-diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
-index 924074f4abe0..03f80cdfffe3 100644
---- a/include/linux/soc/ti/ti_sci_protocol.h
-+++ b/include/linux/soc/ti/ti_sci_protocol.h
-@@ -220,6 +220,9 @@ struct ti_sci_rm_core_ops {
- 				    u16 *range_start, u16 *range_num);
- };
- 
-+#define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT		0
-+#define TI_SCI_RESASG_SUBTYPE_IA_VINT		0xa
-+#define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT	0xd
- /**
-  * struct ti_sci_rm_irq_ops: IRQ management operations
-  * @set_direct_irq:		Set Non-event Sourced direct irq to destination
-@@ -606,6 +609,9 @@ void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
- struct ti_sci_resource *
- devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
- 			    struct device *dev, u32 dev_id, char *of_prop);
-+struct ti_sci_resource *
-+devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
-+			 u32 dev_id, u32 sub_type);
- 
- #else	/* CONFIG_TI_SCI_PROTOCOL */
- 
-@@ -654,6 +660,13 @@ devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
- {
- 	return ERR_PTR(-EINVAL);
- }
-+
-+static inline struct ti_sci_resource *
-+devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
-+			 u32 dev_id, u32 sub_type);
-+{
-+	return ERR_PTR(-EINVAL);
-+}
- #endif	/* CONFIG_TI_SCI_PROTOCOL */
- 
- #endif	/* __TISCI_PROTOCOL_H */
--- 
-2.31.1
-

board/PSG/iot2050/files/0002-firmware-ti_sci-Rework-the-irq_ops-to-configure-inta.patch

@@ -1,623 +0,0 @@
-From 5a58f7c2a08b1df1285f733fac28079b7db3607f Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Tue, 20 Oct 2020 23:28:33 +0530
-Subject: [PATCH 02/26] firmware: ti_sci: Rework the irq_ops to configure inta
- and intr separately
-
-Currently the irq route form IP -> INTA -> INTR -> GIC is configured in
-a single message and happens in inta driver. This will not not work when
-ABI 3.0 is introduced. So, update irq_ops such that INTA configuration
-happens in one message and INTR configuration happens in a different
-message for the above mentioned irq route.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- drivers/firmware/ti_sci.c              | 275 ++++---------------------
- drivers/irqchip/irq-ti-sci-inta.c      |  16 +-
- drivers/irqchip/irq-ti-sci-intr.c      |  25 +--
- include/linux/soc/ti/ti_sci_protocol.h |  87 ++------
- 4 files changed, 67 insertions(+), 336 deletions(-)
-
-diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
-index 72d53423bd20..1b73e7b90d28 100644
---- a/drivers/firmware/ti_sci.c
-+++ b/drivers/firmware/ti_sci.c
-@@ -1884,7 +1884,7 @@ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle,
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-  * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-+ * @dst_host_irq:	IRQ number of the destination device
-  * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-  * @vint:		Virtual interrupt to be used within the IA
-  * @global_event:	Global event number to be used for the requesting event
-@@ -1959,7 +1959,7 @@ static int ti_sci_manage_irq(const struct ti_sci_handle *handle,
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-  * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-+ * @dst_host_irq:	IRQ number of the destination device
-  * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-  * @vint:		Virtual interrupt to be used within the IA
-  * @global_event:	Global event number to be used for the requesting event
-@@ -1993,7 +1993,7 @@ static int ti_sci_set_irq(const struct ti_sci_handle *handle, u32 valid_params,
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-  * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-+ * @dst_host_irq:	IRQ number of the destination device
-  * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-  * @vint:		Virtual interrupt to be used within the IA
-  * @global_event:	Global event number to be used for the requesting event
-@@ -2020,141 +2020,44 @@ static int ti_sci_free_irq(const struct ti_sci_handle *handle, u32 valid_params,
- }
- 
- /**
-- * ti_sci_cmd_set_direct_irq() - Configure a non-event based direct irq route
-- *				 between the requested source and destination.
-+ * ti_sci_cmd_set_irq() - Configure a host irq route between the requested
-+ *			  source and destination.
-  * @handle:		Pointer to TISCI handle.
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-  * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-+ * @dst_host_irq:	IRQ number of the destination device
-+ * @vint_irq:		Boolean specifying if this interrupt belongs to
-+ *			Interrupt Aggregator.
-  *
-  * Return: 0 if all went fine, else return appropriate error.
-  */
--static int ti_sci_cmd_set_direct_irq(const struct ti_sci_handle *handle,
--				     u16 src_id, u16 src_index, u16 dst_id,
--				     u16 dst_host_irq)
-+static int ti_sci_cmd_set_irq(const struct ti_sci_handle *handle, u16 src_id,
-+			      u16 src_index, u16 dst_id, u16 dst_host_irq)
- {
- 	u32 valid_params = MSG_FLAG_DST_ID_VALID | MSG_FLAG_DST_HOST_IRQ_VALID;
- 
--	return ti_sci_set_irq(handle, valid_params, src_id, src_index,
--			      dst_id, dst_host_irq, 0, 0, 0, 0, 0);
--}
--
--/**
-- * ti_sci_cmd_set_event_irq() - Configure an event based irq route between the
-- *				requested source and destination
-- * @handle:		Pointer to TISCI handle.
-- * @src_id:		Device ID of the IRQ source
-- * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-- * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-- * @vint:		Virtual interrupt to be used within the IA
-- * @global_event:	Global event number to be used for the requesting event
-- * @vint_status_bit:	Virtual interrupt status bit to be used for the event
-- *
-- * Return: 0 if all went fine, else return appropriate error.
-- */
--static int ti_sci_cmd_set_event_irq(const struct ti_sci_handle *handle,
--				    u16 src_id, u16 src_index, u16 dst_id,
--				    u16 dst_host_irq, u16 ia_id, u16 vint,
--				    u16 global_event, u8 vint_status_bit)
--{
--	u32 valid_params = MSG_FLAG_DST_ID_VALID |
--			   MSG_FLAG_DST_HOST_IRQ_VALID | MSG_FLAG_IA_ID_VALID |
--			   MSG_FLAG_VINT_VALID | MSG_FLAG_GLB_EVNT_VALID |
--			   MSG_FLAG_VINT_STS_BIT_VALID;
--
- 	return ti_sci_set_irq(handle, valid_params, src_id, src_index, dst_id,
--			      dst_host_irq, ia_id, vint, global_event,
--			      vint_status_bit, 0);
--}
--
--/**
-- * ti_sci_cmd_set_direct_irq_from_shost() - Configure a non-event based direct
-- *					    irq route between the source and
-- *					    destination belonging to a
-- *					    specified host.
-- * @handle:		Pointer to TISCI handle.
-- * @src_id:		Device ID of the IRQ source
-- * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-- * @s_host:		Secondary host ID to which the irq/event is being
-- *			requested for.
-- *
-- * Return: 0 if all went fine, else return appropriate error.
-- */
--static
--int ti_sci_cmd_set_direct_irq_from_shost(const struct ti_sci_handle *handle,
--					 u16 src_id, u16 src_index, u16 dst_id,
--					 u16 dst_host_irq, u8 s_host)
--{
--	u32 valid_params = MSG_FLAG_DST_ID_VALID | MSG_FLAG_DST_HOST_IRQ_VALID |
--			   MSG_FLAG_SHOST_VALID;
--
--	return ti_sci_set_irq(handle, valid_params, src_id, src_index,
--			      dst_id, dst_host_irq, 0, 0, 0, 0, s_host);
--}
--
--/**
-- * ti_sci_cmd_set_event_irq_from_shost() - Configure an event based irq
-- *					   route between the source and
-- *					   destination belonging to a
-- *					   specified host.
-- * @handle:		Pointer to TISCI handle.
-- * @src_id:		Device ID of the IRQ source
-- * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-- * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-- * @vint:		Virtual interrupt to be used within the IA
-- * @global_event:	Global event number to be used for the requesting event
-- * @vint_status_bit:	Virtual interrupt status bit to be used for the event
-- * @s_host:		Secondary host ID to which the irq/event is being
-- *			requested for.
-- *
-- * Return: 0 if all went fine, else return appropriate error.
-- */
--static
--int ti_sci_cmd_set_event_irq_from_shost(const struct ti_sci_handle *handle,
--					u16 src_id, u16 src_index, u16 dst_id,
--					u16 dst_host_irq, u16 ia_id, u16 vint,
--					u16 global_event, u8 vint_status_bit,
--					u8 s_host)
--{
--	u32 valid_params = MSG_FLAG_DST_ID_VALID |
--			   MSG_FLAG_DST_HOST_IRQ_VALID | MSG_FLAG_IA_ID_VALID |
--			   MSG_FLAG_VINT_VALID | MSG_FLAG_GLB_EVNT_VALID |
--			   MSG_FLAG_VINT_STS_BIT_VALID | MSG_FLAG_SHOST_VALID;
--
--	return ti_sci_set_irq(handle, valid_params, src_id, src_index,
--			      dst_id, dst_host_irq, ia_id, vint,
--			      global_event, vint_status_bit, s_host);
-+			      dst_host_irq, 0, 0, 0, 0, 0);
- }
- 
- /**
-- * ti_sci_cmd_set_event_irq_to_poll() - Configure an event based irq
-- *					in polling mode
-+ * ti_sci_cmd_set_event_map() - Configure an event based irq route between the
-+ *				requested source and Interrupt Aggregator.
-  * @handle:		Pointer to TISCI handle.
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-  * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-  * @vint:		Virtual interrupt to be used within the IA
-  * @global_event:	Global event number to be used for the requesting event
-  * @vint_status_bit:	Virtual interrupt status bit to be used for the event
-- * @s_host:		Secondary host ID to which the irq/event is being
-- *			requested for.
-  *
-  * Return: 0 if all went fine, else return appropriate error.
-  */
--static int ti_sci_cmd_set_event_irq_to_poll(const struct ti_sci_handle *handle,
--					    u16 src_id, u16 src_index,
--					    u16 ia_id, u16 vint,
--					    u16 global_event,
--					    u8 vint_status_bit)
-+static int ti_sci_cmd_set_event_map(const struct ti_sci_handle *handle,
-+				    u16 src_id, u16 src_index, u16 ia_id,
-+				    u16 vint, u16 global_event,
-+				    u8 vint_status_bit)
- {
- 	u32 valid_params = MSG_FLAG_IA_ID_VALID | MSG_FLAG_VINT_VALID |
- 			   MSG_FLAG_GLB_EVNT_VALID |
-@@ -2165,34 +2068,33 @@ static int ti_sci_cmd_set_event_irq_to_poll(const struct ti_sci_handle *handle,
- }
- 
- /**
-- * ti_sci_cmd_free_direct_irq() - Free a non-event based direct irq route
-- *				  between the requested source and destination.
-+ * ti_sci_cmd_free_irq() - Free a host irq route between the between the
-+ *			   requested source and destination.
-  * @handle:		Pointer to TISCI handle.
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-  * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-+ * @dst_host_irq:	IRQ number of the destination device
-+ * @vint_irq:		Boolean specifying if this interrupt belongs to
-+ *			Interrupt Aggregator.
-  *
-  * Return: 0 if all went fine, else return appropriate error.
-  */
--static int ti_sci_cmd_free_direct_irq(const struct ti_sci_handle *handle,
--				      u16 src_id, u16 src_index, u16 dst_id,
--				      u16 dst_host_irq)
-+static int ti_sci_cmd_free_irq(const struct ti_sci_handle *handle, u16 src_id,
-+			       u16 src_index, u16 dst_id, u16 dst_host_irq)
- {
- 	u32 valid_params = MSG_FLAG_DST_ID_VALID | MSG_FLAG_DST_HOST_IRQ_VALID;
- 
--	return ti_sci_free_irq(handle, valid_params, src_id, src_index,
--			       dst_id, dst_host_irq, 0, 0, 0, 0, 0);
-+	return ti_sci_free_irq(handle, valid_params, src_id, src_index, dst_id,
-+			       dst_host_irq, 0, 0, 0, 0, 0);
- }
- 
- /**
-- * ti_sci_cmd_free_event_irq() - Free an event based irq route between the
-- *				 requested source and destination
-+ * ti_sci_cmd_free_event_map() - Free an event map between the requested source
-+ *				 and Interrupt Aggregator.
-  * @handle:		Pointer to TISCI handle.
-  * @src_id:		Device ID of the IRQ source
-  * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-  * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-  * @vint:		Virtual interrupt to be used within the IA
-  * @global_event:	Global event number to be used for the requesting event
-@@ -2200,111 +2102,15 @@ static int ti_sci_cmd_free_direct_irq(const struct ti_sci_handle *handle,
-  *
-  * Return: 0 if all went fine, else return appropriate error.
-  */
--static int ti_sci_cmd_free_event_irq(const struct ti_sci_handle *handle,
--				     u16 src_id, u16 src_index, u16 dst_id,
--				     u16 dst_host_irq, u16 ia_id, u16 vint,
--				     u16 global_event, u8 vint_status_bit)
-+static int ti_sci_cmd_free_event_map(const struct ti_sci_handle *handle,
-+				     u16 src_id, u16 src_index, u16 ia_id,
-+				     u16 vint, u16 global_event,
-+				     u8 vint_status_bit)
- {
--	u32 valid_params = MSG_FLAG_DST_ID_VALID |
--			   MSG_FLAG_DST_HOST_IRQ_VALID | MSG_FLAG_IA_ID_VALID |
-+	u32 valid_params = MSG_FLAG_IA_ID_VALID |
- 			   MSG_FLAG_VINT_VALID | MSG_FLAG_GLB_EVNT_VALID |
- 			   MSG_FLAG_VINT_STS_BIT_VALID;
- 
--	return ti_sci_free_irq(handle, valid_params, src_id, src_index,
--			       dst_id, dst_host_irq, ia_id, vint,
--			       global_event, vint_status_bit, 0);
--}
--
--/**
-- * ti_sci_cmd_free_direct_irq_from_shost() - Free a non-event based direct irq
-- *					     route between the source and
-- *					     destination belonging to a
-- *					     specified host.
-- * @handle:		Pointer to TISCI handle.
-- * @src_id:		Device ID of the IRQ source
-- * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-- * @s_host:		Secondary host ID to which the irq/event is being
-- *			requested for.
-- *
-- * Return: 0 if all went fine, else return appropriate error.
-- */
--static
--int ti_sci_cmd_free_direct_irq_from_shost(const struct ti_sci_handle *handle,
--					  u16 src_id, u16 src_index, u16 dst_id,
--					  u16 dst_host_irq, u8 s_host)
--{
--	u32 valid_params = MSG_FLAG_DST_ID_VALID | MSG_FLAG_DST_HOST_IRQ_VALID |
--			   MSG_FLAG_SHOST_VALID;
--
--	return ti_sci_free_irq(handle, valid_params, src_id, src_index,
--			       dst_id, dst_host_irq, 0, 0, 0, 0, s_host);
--}
--
--/**
-- * ti_sci_cmd_free_event_irq_from_shost() - Free an event based irq
-- *					    route between the source and
-- *					    destination belonging to a
-- *					    specified host.
-- * @handle:		Pointer to TISCI handle.
-- * @src_id:		Device ID of the IRQ source
-- * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-- * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-- * @vint:		Virtual interrupt to be used within the IA
-- * @global_event:	Global event number to be used for the requesting event
-- * @vint_status_bit:	Virtual interrupt status bit to be used for the event
-- * @s_host:		Secondary host ID to which the irq/event is being
-- *			requested for.
-- *
-- * Return: 0 if all went fine, else return appropriate error.
-- */
--static
--int ti_sci_cmd_free_event_irq_from_shost(const struct ti_sci_handle *handle,
--					 u16 src_id, u16 src_index, u16 dst_id,
--					 u16 dst_host_irq, u16 ia_id, u16 vint,
--					 u16 global_event, u8 vint_status_bit,
--					 u8 s_host)
--{
--	u32 valid_params = MSG_FLAG_DST_ID_VALID |
--			   MSG_FLAG_DST_HOST_IRQ_VALID | MSG_FLAG_IA_ID_VALID |
--			   MSG_FLAG_VINT_VALID | MSG_FLAG_GLB_EVNT_VALID |
--			   MSG_FLAG_VINT_STS_BIT_VALID | MSG_FLAG_SHOST_VALID;
--
--	return ti_sci_free_irq(handle, valid_params, src_id, src_index,
--			       dst_id, dst_host_irq, ia_id, vint,
--			       global_event, vint_status_bit, s_host);
--}
--
--/**
-- * ti_sci_cmd_free_event_irq_to_poll() - Free an event based irq
-- *					 in polling mode
-- * @handle:		Pointer to TISCI handle.
-- * @src_id:		Device ID of the IRQ source
-- * @src_index:		IRQ source index within the source device
-- * @dst_id:		Device ID of the IRQ destination
-- * @dt_host_irq:	IRQ number of the destination device
-- * @ia_id:		Device ID of the IA, if the IRQ flows through this IA
-- * @vint:		Virtual interrupt to be used within the IA
-- * @global_event:	Global event number to be used for the requesting event
-- * @vint_status_bit:	Virtual interrupt status bit to be used for the event
-- * @s_host:		Secondary host ID to which the irq/event is being
-- *			requested for.
-- *
-- * Return: 0 if all went fine, else return appropriate error.
-- */
--static int ti_sci_cmd_free_event_irq_to_poll(const struct ti_sci_handle *handle,
--					     u16 src_id, u16 src_index,
--					     u16 ia_id, u16 vint,
--					     u16 global_event,
--					     u8 vint_status_bit)
--{
--	u32 valid_params = MSG_FLAG_IA_ID_VALID | MSG_FLAG_VINT_VALID |
--			   MSG_FLAG_GLB_EVNT_VALID |
--			   MSG_FLAG_VINT_STS_BIT_VALID;
--
- 	return ti_sci_free_irq(handle, valid_params, src_id, src_index, 0, 0,
- 			       ia_id, vint, global_event, vint_status_bit, 0);
- }
-@@ -3127,17 +2933,10 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
- 	rm_core_ops->get_range_from_shost =
- 				ti_sci_cmd_get_resource_range_from_shost;
- 
--	iops->set_direct_irq = ti_sci_cmd_set_direct_irq;
--	iops->set_event_irq = ti_sci_cmd_set_event_irq;
--	iops->set_direct_irq_from_shost = ti_sci_cmd_set_direct_irq_from_shost;
--	iops->set_event_irq_from_shost = ti_sci_cmd_set_event_irq_from_shost;
--	iops->set_event_irq_to_poll = ti_sci_cmd_set_event_irq_to_poll;
--	iops->free_direct_irq = ti_sci_cmd_free_direct_irq;
--	iops->free_event_irq = ti_sci_cmd_free_event_irq;
--	iops->free_direct_irq_from_shost =
--					ti_sci_cmd_free_direct_irq_from_shost;
--	iops->free_event_irq_from_shost = ti_sci_cmd_free_event_irq_from_shost;
--	iops->free_event_irq_to_poll = ti_sci_cmd_free_event_irq_to_poll;
-+	iops->set_irq = ti_sci_cmd_set_irq;
-+	iops->set_event_map = ti_sci_cmd_set_event_map;
-+	iops->free_irq = ti_sci_cmd_free_irq;
-+	iops->free_event_map = ti_sci_cmd_free_event_map;
- 
- 	pops->request = ti_sci_cmd_proc_request;
- 	pops->release = ti_sci_cmd_proc_release;
-diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c
-index 88350b4072b8..2cbb13f876a4 100644
---- a/drivers/irqchip/irq-ti-sci-inta.c
-+++ b/drivers/irqchip/irq-ti-sci-inta.c
-@@ -18,7 +18,6 @@
- #include <linux/soc/ti/ti_sci_protocol.h>
- 
- #define MAX_EVENTS_PER_VINT	64
--#define TI_SCI_EVENT_IRQ	BIT(31)
- 
- #define VINT_ENABLE_CLR_OFFSET	0x18
- 
-@@ -151,11 +150,9 @@ static void ti_sci_free_event_irq(struct ti_sci_inta_irq_domain *inta,
- 		return;
- 
- 	event = &vint_desc->events[event_index];
--	inta->sci->ops.rm_irq_ops.free_event_irq(inta->sci,
-+	inta->sci->ops.rm_irq_ops.free_event_map(inta->sci,
- 						 event->src_id,
- 						 event->src_index,
--						 inta->dst_id,
--						 dst_irq,
- 						 inta->ia_id, vint,
- 						 event->global_event,
- 						 event_index);
-@@ -234,18 +231,15 @@ static int ti_sci_allocate_event_irq(struct ti_sci_inta_irq_domain *inta,
- 	event->src_index = src_index;
- 	event->global_event = ti_sci_get_free_resource(inta->global_event);
- 
--	err = inta->sci->ops.rm_irq_ops.set_event_irq(inta->sci,
-+	err = inta->sci->ops.rm_irq_ops.set_event_map(inta->sci,
- 						      src_id, src_index,
--						      inta->dst_id,
--						      dst_irq,
- 						      inta->ia_id,
- 						      vint,
- 						      event->global_event,
- 						      free_bit);
- 	if (err) {
--		pr_err("%s: Event allocation failed from src = %d, index = %d, to dst = %d,irq = %d,via ia_id = %d, vint = %d,global event = %d, status_bit = %d\n",
--		       __func__, src_id, src_index, inta->dst_id, dst_irq,
--		       inta->ia_id, vint, event->global_event, free_bit);
-+		pr_err("%s: Event allocation failed from src = %d, index = %d, to  ia_id = %d, vint = %d,global event = %d, status_bit = %d\n",
-+		       __func__, src_id, src_index, inta->ia_id, vint, event->global_event, free_bit);
- 		return err;
- 	}
- 
-@@ -295,7 +289,7 @@ static struct ti_sci_inta_vint_desc *alloc_parent_irq(struct irq_domain *domain,
- 	/* Interrupt parent is Interrupt Router */
- 	fwspec.param[0] = inta->ia_id;
- 	fwspec.param[1] = vint;
--	fwspec.param[2] = flags | TI_SCI_EVENT_IRQ;
-+	fwspec.param[2] = flags;
- 
- 	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
- 	if (err)
-diff --git a/drivers/irqchip/irq-ti-sci-intr.c b/drivers/irqchip/irq-ti-sci-intr.c
-index a8e141839a42..d7a909a01344 100644
---- a/drivers/irqchip/irq-ti-sci-intr.c
-+++ b/drivers/irqchip/irq-ti-sci-intr.c
-@@ -21,7 +21,6 @@
- #define TI_SCI_DEV_ID_SHIFT	16
- #define TI_SCI_IRQ_ID_MASK	0xffff
- #define TI_SCI_IRQ_ID_SHIFT	0
--#define TI_SCI_IS_EVENT_IRQ	BIT(31)
- 
- #define HWIRQ_TO_DEVID(hwirq)	(((hwirq) >> (TI_SCI_DEV_ID_SHIFT)) & \
- 				 (TI_SCI_DEV_ID_MASK))
-@@ -84,8 +83,8 @@ static inline void ti_sci_intr_delete_desc(struct ti_sci_intr_irq_domain *intr,
- 					   u16 src_id, u16 src_index,
- 					   u16 dst_irq)
- {
--	intr->sci->ops.rm_irq_ops.free_direct_irq(intr->sci, src_id, src_index,
--						  intr->dst_id, dst_irq);
-+	intr->sci->ops.rm_irq_ops.free_irq(intr->sci, src_id, src_index,
-+					   intr->dst_id, dst_irq);
- }
- 
- /**
-@@ -99,21 +98,16 @@ static void ti_sci_intr_irq_domain_free(struct irq_domain *domain,
- {
- 	struct ti_sci_intr_irq_domain *intr = domain->host_data;
- 	struct irq_data *data, *parent_data;
--	u32 flags;
- 	int i;
- 
- 	intr = domain->host_data;
- 
- 	for (i = 0; i < nr_irqs; i++) {
- 		data = irq_domain_get_irq_data(domain, virq + i);
--		flags = (u32)(u64)irq_data_get_irq_chip_data(data);
- 		parent_data = irq_domain_get_irq_data(domain->parent, virq + i);
- 
--		if (!(flags & TI_SCI_IS_EVENT_IRQ))
--			ti_sci_intr_delete_desc(intr,
--						HWIRQ_TO_DEVID(data->hwirq),
--						HWIRQ_TO_IRQID(data->hwirq),
--						parent_data->hwirq);
-+		ti_sci_intr_delete_desc(intr, HWIRQ_TO_DEVID(data->hwirq),
-+					HWIRQ_TO_IRQID(data->hwirq), parent_data->hwirq);
- 		ti_sci_release_resource(intr->dst_irq, parent_data->hwirq);
- 		irq_domain_free_irqs_parent(domain, virq + i, 1);
- 		irq_domain_reset_irq_data(data);
-@@ -152,12 +146,8 @@ static int allocate_gic_irq(struct irq_domain *domain, unsigned int virq,
- 	if (err)
- 		goto err_irqs;
- 
--	/* If event is requested then return */
--	if (flags & TI_SCI_IS_EVENT_IRQ)
--		return 0;
--
--	err = intr->sci->ops.rm_irq_ops.set_direct_irq(intr->sci, dev, irq,
--						       intr->dst_id, dst_irq);
-+	err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci, dev, irq,
-+						intr->dst_id, dst_irq);
- 	if (err) {
- 		pr_err("%s: IRQ allocation failed from src = %d, src_index = %d to dst_id = %d, dst_irq = %d",
- 		       __func__, dev, irq, intr->dst_id, dst_irq);
-@@ -206,8 +196,7 @@ static int ti_sci_intr_irq_domain_alloc(struct irq_domain *domain,
- 			goto err_irq;
- 
- 		err = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
--						    &ti_sci_intr_irq_chip,
--						    (void *)(u64)type);
-+						    &ti_sci_intr_irq_chip, NULL);
- 		if (err)
- 			goto err_irq;
- 	}
-diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
-index 03f80cdfffe3..c05502bf337a 100644
---- a/include/linux/soc/ti/ti_sci_protocol.h
-+++ b/include/linux/soc/ti/ti_sci_protocol.h
-@@ -225,77 +225,26 @@ struct ti_sci_rm_core_ops {
- #define TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT	0xd
- /**
-  * struct ti_sci_rm_irq_ops: IRQ management operations
-- * @set_direct_irq:		Set Non-event Sourced direct irq to destination
-- *				host(same host as ti sci interface id).
-- * @set_event_irq:		Set Event based peripheral irq to destination
-- *				host(same host as ti sci interface id).
-- * @set_direct_irq_from_shost:	Set Non-event Sourced direct irq to a
-- *				specified destination host.
-- * @set_event_irq_from_shost:	Set Event based peripheral irq to a
-- *				specified destination host.
-- * @set_event_irq_to_poll:	Set Event based peripheral irq to polling mode.
-- *				vint_status_bit is used for polling.
-- * @free_direct_irq:		Free a non-event sourced direct irq to
-- *				destination host(same as ti sci interface id)
-- * @free_event_irq:		Free an event based peripheral irq to
-- *				destination host(same as ti sci interface id)
-- * @free_direct_irq_from_shost:	Free non-event based direct irq from a
-- *				specified destination host.
-- * @free_event_irq_from_shost:	Free event based peripheral irq from a
-- *				specified destination host.
-- * @free_event_irq_to_poll:	Free an event based peripheral irq that is
-- *				configured in polling mode.
-- *
-- * NOTE: for these functions, all the parameters are consolidated and defined
-- * as below:
-- * - handle:	Pointer to TISCI handle as retrieved by *ti_sci_get_handle
-- * - src_id:	Device ID of the IRQ source
-- * - src_index:	IRQ source index within the source device
-- * - dst_id:	Device ID of the IRQ destination.
-- * - dst_host_irq:	IRQ number of the destination device.
-- * - ia_id:	Device ID of the IA, if the IRQ flows through this IA
-- * - vint:	Virtual interrupt to be used within the IA
-- * - global_event:	Global event number to be used for the requesting event.
-- * - vint_status_bit:	Virtual interrupt status bit to be used for the event.
-- * - s_host:	Secondary host ID to which the irq/event is being requested.
-+ * @set_irq:		Set an IRQ route between the requested source
-+ *			and destination
-+ * @set_event_map:	Set an Event based peripheral irq to Interrupt
-+ *			Aggregator.
-+ * @free_irq:		Free an IRQ route between the requested source
-+ *			and destination.
-+ * @free_event_map:	Free an event based peripheral irq to Interrupt
-+ *			Aggregator.
-  */
- struct ti_sci_rm_irq_ops {
--	int (*set_direct_irq)(const struct ti_sci_handle *handle, u16 src_id,
--			      u16 src_index, u16 dst_id, u16 dst_host_irq);
--	int (*set_event_irq)(const struct ti_sci_handle *handle, u16 src_id,
--			     u16 src_index, u16 dst_id, u16 dst_host_irq,
--			     u16 ia_id, u16 vint, u16 global_event,
--			     u8 vint_status_bit);
--	int (*set_direct_irq_from_shost)(const struct ti_sci_handle *handle,
--					 u16 src_id, u16 src_index, u16 dst_id,
--					 u16 dst_host_irq, u8 s_host);
--	int (*set_event_irq_from_shost)(const struct ti_sci_handle *handle,
--					u16 src_id, u16 src_index, u16 dst_id,
--					u16 dst_host_irq, u16 ia_id, u16 vint,
--					u16 global_event, u8 vint_status_bit,
--					u8 s_host);
--	int (*set_event_irq_to_poll)(const struct ti_sci_handle *handle,
--				     u16 src_id, u16 src_index, u16 ia_id,
--				     u16 vint, u16 global_event,
--				     u8 vint_status_bit);
--	int (*free_direct_irq)(const struct ti_sci_handle *handle, u16 src_id,
--			       u16 src_index, u16 dst_id, u16 dst_host_irq);
--	int (*free_event_irq)(const struct ti_sci_handle *handle, u16 src_id,
--			      u16 src_index, u16 dst_id, u16 dst_host_irq,
--			      u16 ia_id, u16 vint, u16 global_event,
--			      u8 vint_status_bit);
--	int (*free_direct_irq_from_shost)(const struct ti_sci_handle *handle,
--					  u16 src_id, u16 src_index, u16 dst_id,
--					  u16 dst_host_irq, u8 s_host);
--	int (*free_event_irq_from_shost)(const struct ti_sci_handle *handle,
--					 u16 src_id, u16 src_index, u16 dst_id,
--					 u16 dst_host_irq, u16 ia_id, u16 vint,
--					 u16 global_event, u8 vint_status_bit,
--					 u8 s_host);
--	int (*free_event_irq_to_poll)(const struct ti_sci_handle *handle,
--				      u16 src_id, u16 src_index, u16 ia_id,
--				      u16 vint, u16 global_event,
--				      u8 vint_status_bit);
-+	int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
-+		       u16 src_index, u16 dst_id, u16 dst_host_irq);
-+	int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
-+			     u16 src_index, u16 ia_id, u16 vint,
-+			     u16 global_event, u8 vint_status_bit);
-+	int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
-+			u16 src_index, u16 dst_id, u16 dst_host_irq);
-+	int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
-+			      u16 src_index, u16 ia_id, u16 vint,
-+			      u16 global_event, u8 vint_status_bit);
- };
- 
- /**
--- 
-2.31.1
-

board/PSG/iot2050/files/0003-firmware-ti_sci-Use-dev_id-as-resource-type-with-ABI.patch

@@ -1,85 +0,0 @@
-From 9cc9c0a3788ed165ba1efeac2543e9162f20325d Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Tue, 20 Oct 2020 16:07:40 +0530
-Subject: [PATCH 03/26] firmware: ti_sci: Use dev_id as resource type with ABI
- 3.0
-
-With ABI 3.0, sysfw deprecated special resource types used for AM65x
-SoC. So, make ti_sci_get_resource_type() to return resource type as
-devid if ABI 3.0 is detected.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- drivers/firmware/ti_sci.c              | 17 ++++++++++++++---
- include/linux/soc/ti/ti_sci_protocol.h |  6 ++++++
- 2 files changed, 20 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
-index 1b73e7b90d28..4b21139f5195 100644
---- a/drivers/firmware/ti_sci.c
-+++ b/drivers/firmware/ti_sci.c
-@@ -1729,6 +1729,15 @@ static int ti_sci_cmd_core_reboot(const struct ti_sci_handle *handle)
- 	return ret;
- }
- 
-+bool ti_sci_abi_3_and_above(const struct ti_sci_handle *handle)
-+{
-+	if (handle->version.abi_major >= 3)
-+		return true;
-+	else
-+		return false;
-+}
-+EXPORT_SYMBOL_GPL(ti_sci_abi_3_and_above);
-+
- static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
- 				    u16 *type)
- {
-@@ -1736,8 +1745,11 @@ static int ti_sci_get_resource_type(struct ti_sci_info *info, u16 dev_id,
- 	bool found = false;
- 	int i;
- 
--	/* If map is not provided then assume dev_id is used as type */
--	if (!rm_type_map) {
-+	/*
-+	 * - If map is not provided then assume dev_id is used as type.
-+	 * - With abi 3.0, sysfw depricated special resource types. use dev_id as type.
-+	 */
-+	if (!rm_type_map || ti_sci_abi_3_and_above(&info->handle)) {
- 		*type = dev_id;
- 		return 0;
- 	}
-@@ -3246,7 +3258,6 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
- 			      struct device *dev, u32 dev_id, u32 *sub_types,
- 			      u32 sets)
- {
--	u32 resource_subtype;
- 	u16 resource_type;
- 	struct ti_sci_resource *res;
- 	bool valid_set = false;
-diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
-index c05502bf337a..1adb93d5ca03 100644
---- a/include/linux/soc/ti/ti_sci_protocol.h
-+++ b/include/linux/soc/ti/ti_sci_protocol.h
-@@ -562,6 +562,7 @@ struct ti_sci_resource *
- devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
- 			 u32 dev_id, u32 sub_type);
- 
-+bool ti_sci_abi_3_and_above(const struct ti_sci_handle *handle);
- #else	/* CONFIG_TI_SCI_PROTOCOL */
- 
- static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
-@@ -616,6 +617,11 @@ devm_ti_sci_get_resource(const struct ti_sci_handle *handle, struct device *dev,
- {
- 	return ERR_PTR(-EINVAL);
- }
-+
-+static inline bool ti_sci_abi_3_and_above(const struct ti_sci_handle *handle)
-+{
-+	return false;
-+}
- #endif	/* CONFIG_TI_SCI_PROTOCOL */
- 
- #endif	/* __TISCI_PROTOCOL_H */
--- 
-2.31.1
-

board/PSG/iot2050/files/0004-irqchip-ti-sci-inta-Add-ABI-3.0-support.patch

@@ -1,159 +0,0 @@
-From 30d2866184a6c8a8c476ab61b48679faf17d820b Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Tue, 20 Oct 2020 18:59:31 +0530
-Subject: [PATCH 04/26] irqchip/ti-sci-inta: Add ABI 3.0 support
-
-Update the inta driver to include support for ABI 3.0
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- drivers/irqchip/irq-ti-sci-inta.c | 101 +++++++++++++++++++++++-------
- 1 file changed, 80 insertions(+), 21 deletions(-)
-
-diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c
-index 2cbb13f876a4..36644b29248b 100644
---- a/drivers/irqchip/irq-ti-sci-inta.c
-+++ b/drivers/irqchip/irq-ti-sci-inta.c
-@@ -36,6 +36,7 @@ struct ti_sci_inta_irq_domain {
- 	struct ti_sci_resource *vint;
- 	struct ti_sci_resource *global_event;
- 	void __iomem *base;
-+	struct device *dev;
- 	u16 ia_id;
- 	u16 dst_id;
- };
-@@ -194,6 +195,37 @@ static void ti_sci_inta_irq_domain_free(struct irq_domain *domain,
- 	kfree(vint_desc);
- }
- 
-+/**
-+ * ti_sci_inta_xlate_irq() - Translate hwirq to parent's hwirq.
-+ * @inta:	IRQ domain corresponding to Interrupt Aggregator
-+ * @irq:	Hardware irq corresponding to the above irq domain
-+ *
-+ * Return parent irq number if translation is available else -ENOENT.
-+ */
-+static int ti_sci_inta_xlate_irq(struct ti_sci_inta_irq_domain *inta,
-+				 u16 vint_id)
-+{
-+	struct device_node *np = dev_of_node(inta->dev);
-+	u32 base, parent_base, size;
-+	const __be32 *range;
-+	int len;
-+
-+	range = of_get_property(np, "ti,interrupt-ranges", &len);
-+	if (!range)
-+		return vint_id;
-+
-+	for (len /= sizeof(*range); len >= 3; len -= 3) {
-+		base = be32_to_cpu(*range++);
-+		parent_base = be32_to_cpu(*range++);
-+		size = be32_to_cpu(*range++);
-+
-+		if (base <= vint_id && vint_id < base + size)
-+			return vint_id - base + parent_base;
-+	}
-+
-+	return -ENOENT;
-+}
-+
- /**
-  * ti_sci_allocate_event_irq() - Allocate an event to a IA vint.
-  * @inta:	Pointer to Interrupt Aggregator IRQ domain
-@@ -267,11 +299,18 @@ static struct ti_sci_inta_vint_desc *alloc_parent_irq(struct irq_domain *domain,
- 	struct ti_sci_inta_vint_desc *vint_desc;
- 	struct irq_data *gic_data;
- 	struct irq_fwspec fwspec;
--	int err;
-+	int err, p_hwirq;
- 
- 	if (!irq_domain_get_of_node(domain->parent))
- 		return ERR_PTR(-EINVAL);
- 
-+	p_hwirq = vint;
-+	if (ti_sci_abi_3_and_above(inta->sci)) {
-+		p_hwirq = ti_sci_inta_xlate_irq(inta, vint);
-+		if (p_hwirq < 0)
-+			return ERR_PTR(p_hwirq);
-+	}
-+
- 	vint_desc = kzalloc(sizeof(*vint_desc), GFP_KERNEL);
- 	if (!vint_desc)
- 		return ERR_PTR(-ENOMEM);
-@@ -285,11 +324,17 @@ static struct ti_sci_inta_vint_desc *alloc_parent_irq(struct irq_domain *domain,
- 	}
- 
- 	fwspec.fwnode = domain->parent->fwnode;
--	fwspec.param_count = 3;
--	/* Interrupt parent is Interrupt Router */
--	fwspec.param[0] = inta->ia_id;
--	fwspec.param[1] = vint;
--	fwspec.param[2] = flags;
-+	if (ti_sci_abi_3_and_above(inta->sci)) {
-+		/* Parent is Interrupt Router */
-+		fwspec.param_count = 1;
-+		fwspec.param[0] = p_hwirq;
-+	} else {
-+		fwspec.param_count = 3;
-+		/* Interrupt parent is Interrupt Router */
-+		fwspec.param[0] = inta->ia_id;
-+		fwspec.param[1] = vint;
-+		fwspec.param[2] = flags;
-+	}
- 
- 	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
- 	if (err)
-@@ -388,21 +433,35 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev)
- 		return -EINVAL;
- 	}
- 
--	inta->vint = devm_ti_sci_get_of_resource(inta->sci, dev,
--						 inta->ia_id,
--						 "ti,sci-rm-range-vint");
--	if (IS_ERR(inta->vint)) {
--		dev_err(dev, "VINT resource allocation failed\n");
--		return PTR_ERR(inta->vint);
--	}
--
--	inta->global_event =
--		devm_ti_sci_get_of_resource(inta->sci, dev,
--					    inta->ia_id,
--					    "ti,sci-rm-range-global-event");
--	if (IS_ERR(inta->global_event)) {
--		dev_err(dev, "Global event resource allocation failed\n");
--		return PTR_ERR(inta->global_event);
-+	inta->dev = dev;
-+	if (ti_sci_abi_3_and_above(inta->sci)) {
-+		inta->vint = devm_ti_sci_get_resource(inta->sci, dev, inta->ia_id,
-+						      TI_SCI_RESASG_SUBTYPE_IA_VINT);
-+		if (IS_ERR(inta->vint)) {
-+			dev_err(dev, "VINT resource allocation failed\n");
-+			return PTR_ERR(inta->vint);
-+		}
-+
-+		inta->global_event = devm_ti_sci_get_resource(inta->sci, dev, inta->ia_id,
-+						      TI_SCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT);
-+		if (IS_ERR(inta->global_event)) {
-+			dev_err(dev, "Global event resource allocation failed\n");
-+			return PTR_ERR(inta->global_event);
-+		}
-+	} else {
-+		inta->vint = devm_ti_sci_get_of_resource(inta->sci, dev, inta->ia_id,
-+							 "ti,sci-rm-range-vint");
-+		if (IS_ERR(inta->vint)) {
-+			dev_err(dev, "VINT resource allocation failed\n");
-+			return PTR_ERR(inta->vint);
-+		}
-+
-+		inta->global_event = devm_ti_sci_get_of_resource(inta->sci, dev, inta->ia_id,
-+							    "ti,sci-rm-range-global-event");
-+		if (IS_ERR(inta->global_event)) {
-+			dev_err(dev, "Global event resource allocation failed\n");
-+			return PTR_ERR(inta->global_event);
-+		}
- 	}
- 
- 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--- 
-2.31.1
-

board/PSG/iot2050/files/0005-irqchip-ti-sci-intr-Add-ABI-3.0-support.patch

@@ -1,290 +0,0 @@
-From 7014352fb2af049c7eb470706f1718e146c146cf Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Wed, 21 Oct 2020 00:47:38 +0530
-Subject: [PATCH 05/26] irqchip/ti-sci-intr: Add ABI 3.0 support
-
-Update the intr driver to include support for ABI 3.0
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- drivers/irqchip/irq-ti-sci-intr.c | 198 ++++++++++++++++++++----------
- 1 file changed, 132 insertions(+), 66 deletions(-)
-
-diff --git a/drivers/irqchip/irq-ti-sci-intr.c b/drivers/irqchip/irq-ti-sci-intr.c
-index d7a909a01344..2542da99a78c 100644
---- a/drivers/irqchip/irq-ti-sci-intr.c
-+++ b/drivers/irqchip/irq-ti-sci-intr.c
-@@ -37,6 +37,8 @@ struct ti_sci_intr_irq_domain {
- 	const struct ti_sci_handle *sci;
- 	struct ti_sci_resource *dst_irq;
- 	u16 dst_id;
-+	struct device *dev;
-+	u32 type;
- };
- 
- static struct irq_chip ti_sci_intr_irq_chip = {
-@@ -64,7 +66,17 @@ static int ti_sci_intr_irq_domain_translate(struct irq_domain *domain,
- 					    unsigned long *hwirq,
- 					    unsigned int *type)
- {
--	if (is_of_node(fwspec->fwnode)) {
-+	struct ti_sci_intr_irq_domain *intr = domain->host_data;
-+
-+	if (ti_sci_abi_3_and_above(intr->sci)) {
-+		if (fwspec->param_count != 1)
-+			return -EINVAL;
-+
-+		*hwirq = fwspec->param[0];
-+		*type = intr->type;
-+
-+		return 0;
-+	} else {
- 		if (fwspec->param_count != 3)
- 			return -EINVAL;
- 
-@@ -97,69 +109,112 @@ static void ti_sci_intr_irq_domain_free(struct irq_domain *domain,
- 					unsigned int virq, unsigned int nr_irqs)
- {
- 	struct ti_sci_intr_irq_domain *intr = domain->host_data;
--	struct irq_data *data, *parent_data;
--	int i;
-+	int out_irq, src_id, src_index;
-+	struct irq_data *data;
- 
- 	intr = domain->host_data;
- 
--	for (i = 0; i < nr_irqs; i++) {
--		data = irq_domain_get_irq_data(domain, virq + i);
--		parent_data = irq_domain_get_irq_data(domain->parent, virq + i);
-+	data = irq_domain_get_irq_data(domain, virq);
-+	out_irq = (uintptr_t)data->chip_data;
- 
--		ti_sci_intr_delete_desc(intr, HWIRQ_TO_DEVID(data->hwirq),
--					HWIRQ_TO_IRQID(data->hwirq), parent_data->hwirq);
--		ti_sci_release_resource(intr->dst_irq, parent_data->hwirq);
--		irq_domain_free_irqs_parent(domain, virq + i, 1);
--		irq_domain_reset_irq_data(data);
-+	if (ti_sci_abi_3_and_above(intr->sci)) {
-+		src_id = intr->dst_id;
-+		src_index = data->hwirq;
-+	} else {
-+		src_id = HWIRQ_TO_DEVID(data->hwirq);
-+		src_index = HWIRQ_TO_IRQID(data->hwirq);
- 	}
-+
-+	ti_sci_intr_delete_desc(intr, src_id, src_index, out_irq);
-+	ti_sci_release_resource(intr->dst_irq, out_irq);
-+	irq_domain_free_irqs_parent(domain, virq, 1);
-+	irq_domain_reset_irq_data(data);
- }
- 
- /**
-- * allocate_gic_irq() - Allocate GIC specific IRQ
-- * @domain:	Point to the interrupt router IRQ domain
-- * @dev:	TISCI device IRQ generating the IRQ
-- * @irq:	IRQ offset within the device
-- * @flags:	Corresponding flags to the IRQ
-+ * ti_sci_intr_xlate_irq() - Translate hwirq to parent's hwirq.
-+ * @intr:	IRQ domain corresponding to Interrupt Router
-+ * @irq:	Hardware irq corresponding to the above irq domain
-  *
-- * Returns 0 if all went well else appropriate error pointer.
-+ * Return parent irq number if translation is available else -ENOENT.
-  */
--static int allocate_gic_irq(struct irq_domain *domain, unsigned int virq,
--			    u16 dev, u16 irq, u32 flags)
-+static int ti_sci_intr_xlate_irq(struct ti_sci_intr_irq_domain *intr, u32 irq)
-+{
-+	struct device_node *np = dev_of_node(intr->dev);
-+	u32 base, pbase, size, len;
-+	const __be32 *range;
-+
-+	range = of_get_property(np, "ti,interrupt-ranges", &len);
-+	if (!range)
-+		return irq;
-+
-+	for (len /= sizeof(*range); len >= 3; len -= 3) {
-+		base = be32_to_cpu(*range++);
-+		pbase = be32_to_cpu(*range++);
-+		size = be32_to_cpu(*range++);
-+
-+		if (base <= irq && irq < base + size)
-+			return irq - base + pbase;
-+	}
-+
-+	return -ENOENT;
-+}
-+
-+static int ti_sci_intr_alloc_parent_irq(struct irq_domain *domain,
-+					unsigned int virq, u32 hwirq, u32 type)
- {
- 	struct ti_sci_intr_irq_domain *intr = domain->host_data;
-+	struct device_node *parent_node;
-+	u16 out_irq, src_id, src_index;
- 	struct irq_fwspec fwspec;
--	u16 dst_irq;
--	int err;
-+	int p_hwirq, err = 0;
- 
--	if (!irq_domain_get_of_node(domain->parent))
-+	out_irq = ti_sci_get_free_resource(intr->dst_irq);
-+	if (out_irq == TI_SCI_RESOURCE_NULL)
- 		return -EINVAL;
- 
--	dst_irq = ti_sci_get_free_resource(intr->dst_irq);
-+	if (ti_sci_abi_3_and_above(intr->sci)) {
-+		p_hwirq = ti_sci_intr_xlate_irq(intr, out_irq);
-+		if (p_hwirq < 0)
-+			goto err_irqs;
-+		src_id = intr->dst_id;
-+		src_index = hwirq;
-+	} else {
-+		p_hwirq = out_irq;
-+		src_id = HWIRQ_TO_DEVID(hwirq);
-+		src_index = HWIRQ_TO_IRQID(hwirq);
-+	}
- 
--	fwspec.fwnode = domain->parent->fwnode;
--	fwspec.param_count = 3;
--	fwspec.param[0] = 0;	/* SPI */
--	fwspec.param[1] = dst_irq - 32; /* SPI offset */
--	fwspec.param[2] = flags & IRQ_TYPE_SENSE_MASK;
-+	parent_node = of_irq_find_parent(dev_of_node(intr->dev));
-+	fwspec.fwnode = of_node_to_fwnode(parent_node);
-+
-+	if (of_device_is_compatible(parent_node, "arm,gic-v3")) {
-+		/* Parent is GIC */
-+		fwspec.param_count = 3;
-+		fwspec.param[0] = 0;	/* SPI */
-+		fwspec.param[1] = p_hwirq - 32; /* SPI offset */
-+		fwspec.param[2] = type;
-+	} else {
-+		/* Parent is Interrupt Router */
-+		fwspec.param_count = 1;
-+		fwspec.param[0] = p_hwirq;
-+	}
- 
- 	err = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
- 	if (err)
- 		goto err_irqs;
- 
--	err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci, dev, irq,
--						intr->dst_id, dst_irq);
--	if (err) {
--		pr_err("%s: IRQ allocation failed from src = %d, src_index = %d to dst_id = %d, dst_irq = %d",
--		       __func__, dev, irq, intr->dst_id, dst_irq);
-+	err = intr->sci->ops.rm_irq_ops.set_irq(intr->sci, src_id, src_index,
-+						intr->dst_id, out_irq);
-+	if (err)
- 		goto err_msg;
--	}
- 
--	return 0;
-+	return out_irq;
- 
- err_msg:
- 	irq_domain_free_irqs_parent(domain, virq, 1);
- err_irqs:
--	ti_sci_release_resource(intr->dst_irq, dst_irq);
-+	ti_sci_release_resource(intr->dst_irq, out_irq);
- 	return err;
- }
- 
-@@ -177,33 +232,22 @@ static int ti_sci_intr_irq_domain_alloc(struct irq_domain *domain,
- 					void *data)
- {
- 	struct irq_fwspec *fwspec = data;
--	u16 src_id, src_index;
- 	unsigned long hwirq;
--	int i, err;
-+	int err, p_hwirq;
- 	u32 type;
- 
- 	err = ti_sci_intr_irq_domain_translate(domain, fwspec, &hwirq, &type);
- 	if (err)
- 		return err;
- 
--	src_id = HWIRQ_TO_DEVID(hwirq);
--	src_index = HWIRQ_TO_IRQID(hwirq);
-+	p_hwirq = ti_sci_intr_alloc_parent_irq(domain, virq, hwirq, type);
-+	if (p_hwirq < 0)
-+		return p_hwirq;
- 
--	for (i = 0; i < nr_irqs; i++) {
--		err = allocate_gic_irq(domain, virq + i, src_id, src_index + i,
--				       type);
--		if (err)
--			goto err_irq;
-+	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
-+				      &ti_sci_intr_irq_chip,
-+				      (void *)(uintptr_t)p_hwirq);
- 
--		err = irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
--						    &ti_sci_intr_irq_chip, NULL);
--		if (err)
--			goto err_irq;
--	}
--
--	return 0;
--err_irq:
--	ti_sci_intr_irq_domain_free(domain, virq, i);
- 	return err;
- }
- 
-@@ -246,19 +290,41 @@ static int ti_sci_intr_irq_domain_probe(struct platform_device *pdev)
- 		return ret;
- 	}
- 
--	ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dst-id",
--				   (u32 *)&intr->dst_id);
--	if (ret) {
--		dev_err(dev, "missing 'ti,sci-dst-id' property\n");
--		return -EINVAL;
--	}
-+	intr->dev = dev;
-+	if (ti_sci_abi_3_and_above(intr->sci)) {
-+		ret = of_property_read_u32(dev_of_node(dev), "ti,intr-trigger-type", &intr->type);
-+		if (ret) {
-+			dev_err(dev, "missing ti,intr-trigger-type property\n");
-+			return -EINVAL;
-+		}
- 
--	intr->dst_irq = devm_ti_sci_get_of_resource(intr->sci, dev,
--						    intr->dst_id,
--						    "ti,sci-rm-range-girq");
--	if (IS_ERR(intr->dst_irq)) {
--		dev_err(dev, "Destination irq resource allocation failed\n");
--		return PTR_ERR(intr->dst_irq);
-+		ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dev-id", (u32 *)&intr->dst_id);
-+		if (ret) {
-+			dev_err(dev, "missing 'ti,sci-dev-id' property\n");
-+			return -EINVAL;
-+		}
-+
-+		intr->dst_irq = devm_ti_sci_get_resource(intr->sci, dev, intr->dst_id,
-+							  TI_SCI_RESASG_SUBTYPE_IR_OUTPUT);
-+		if (IS_ERR(intr->dst_irq)) {
-+			dev_err(dev, "Destination irq resource allocation failed\n");
-+			return PTR_ERR(intr->dst_irq);
-+		}
-+	} else {
-+		ret = of_property_read_u32(dev_of_node(dev), "ti,sci-dst-id",
-+					   (u32 *)&intr->dst_id);
-+		if (ret) {
-+			dev_err(dev, "missing 'ti,sci-dst-id' property\n");
-+			return -EINVAL;
-+		}
-+
-+		intr->dst_irq = devm_ti_sci_get_of_resource(intr->sci, dev,
-+							    intr->dst_id,
-+							    "ti,sci-rm-range-girq");
-+		if (IS_ERR(intr->dst_irq)) {
-+			dev_err(dev, "Destination irq resource allocation failed\n");
-+			return PTR_ERR(intr->dst_irq);
-+		}
- 	}
- 
- 	domain = irq_domain_add_hierarchy(parent_domain, 0, 0, dev_of_node(dev),
--- 
-2.31.1
-

board/PSG/iot2050/files/0006-HACK-dma-am65x-Update-rchan-oes-offset-with-ABI-3.0.patch

@@ -1,47 +0,0 @@
-From d8c85abd7826d201a1483d11e6c45e39406c8ea8 Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Wed, 21 Oct 2020 01:19:58 +0530
-Subject: [PATCH 06/26] HACK: dma: am65x: Update rchan oes offset with ABI 3.0
-
-Update the rchan oes offset when using ABI 3.0 sysfw.
-
-Note: This patch breaks J721e and that's why its a hack.
-To get j721e support cleanly, k3-socinfo driver from 5.4 kernel
-should be backported. Since, j721e is not targeted here, not doing
-it in a cleaner way and hacking around.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- drivers/dma/ti/k3-udma.c | 9 +++++++--
- 1 file changed, 7 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
-index 0f743a5a6a03..c93c0c0f86b5 100644
---- a/drivers/dma/ti/k3-udma.c
-+++ b/drivers/dma/ti/k3-udma.c
-@@ -1583,6 +1583,7 @@ static int udma_alloc_chan_resources(struct dma_chan *chan)
- 	const struct udma_match_data *match_data = uc->ud->match_data;
- 	struct udma_tchan *tchan;
- 	struct udma_rchan *rchan;
-+	u32 rchan_oes_offset;
- 	int ret;
- 
- 	if (uc->pkt_mode || uc->dir == DMA_MEM_TO_MEM) {
-@@ -1881,8 +1882,12 @@ static int udma_alloc_chan_resources(struct dma_chan *chan)
- 			uc->irq_ra_tisci = k3_ringacc_get_tisci_dev_id(
- 								rchan->r_ring);
- 			uc->irq_ra_idx = rx_ring;
--			uc->irq_udma_idx = match_data->rchan_oes_offset +
--					   rchan->id;
-+			/* ToDo: This will fail for J721E */
-+			if (ti_sci_abi_3_and_above(ud->tisci_rm.tisci))
-+				rchan_oes_offset = 0x200;
-+			else
-+				rchan_oes_offset = match_data->rchan_oes_offset;
-+			uc->irq_udma_idx = rchan_oes_offset + rchan->id;
- 		}
- 	}
- 
--- 
-2.31.1
-

board/PSG/iot2050/files/0007-arm64-dts-ti-k3-am654-Introduce-ABI3.x-specific-dts.patch

@@ -1,219 +0,0 @@
-From 2b3bb7aa6851ea0212e24d00e66548764b8808fb Mon Sep 17 00:00:00 2001
-From: Lokesh Vutla <lokeshvutla@ti.com>
-Date: Wed, 21 Oct 2020 15:25:16 +0530
-Subject: [PATCH 07/26] arm64: dts: ti: k3-am654: Introduce ABI3.x specific dts
-
-Introduce ABI3.x specific dts that supports booting with sysfw ABI 3.x
-and later.
-
-Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
----
- arch/arm64/boot/dts/ti/Makefile               |  1 +
- .../boot/dts/ti/k3-am65-main-abi3_x.dtsi      | 86 +++++++++++++++++++
- arch/arm64/boot/dts/ti/k3-am65-main.dtsi      |  2 +-
- .../arm64/boot/dts/ti/k3-am65-mcu-abi3_x.dtsi | 18 ++++
- .../boot/dts/ti/k3-am65-wakeup-abi3_x.dtsi    | 25 ++++++
- .../dts/ti/k3-am654-base-board-abi3_x.dts     | 16 ++++
- 6 files changed, 147 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/ti/k3-am65-main-abi3_x.dtsi
- create mode 100644 arch/arm64/boot/dts/ti/k3-am65-mcu-abi3_x.dtsi
- create mode 100644 arch/arm64/boot/dts/ti/k3-am65-wakeup-abi3_x.dtsi
- create mode 100644 arch/arm64/boot/dts/ti/k3-am654-base-board-abi3_x.dts
-
-diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
-index ea9474ca5ff5..b952d3e730d6 100644
---- a/arch/arm64/boot/dts/ti/Makefile
-+++ b/arch/arm64/boot/dts/ti/Makefile
-@@ -9,6 +9,7 @@
- DTC_FLAGS += -@
- 
- dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb \
-+	k3-am654-base-board-abi3_x.dtb \
- 	k3-am654-gp.dtbo \
- 	k3-am654-evm-hdmi.dtbo \
- 	k3-am654-evm-oldi-lcd1evm.dtbo \
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-main-abi3_x.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main-abi3_x.dtsi
-new file mode 100644
-index 000000000000..8a83a833094c
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am65-main-abi3_x.dtsi
-@@ -0,0 +1,86 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Device Tree Source for AM6 SoC Family Main Domain peripherals
-+ *
-+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
-+ */
-+
-+&cbass_main {
-+	/delete-node/ main_intr;
-+	
-+	intr_main_gpio: interrupt-controller0 {
-+		compatible = "ti,sci-intr";
-+		ti,intr-trigger-type = <1>;
-+		interrupt-controller;
-+		interrupt-parent = <&gic500>;
-+		#interrupt-cells = <1>;
-+		ti,sci = <&dmsc>;
-+		ti,sci-dev-id = <100>;
-+		ti,interrupt-ranges = <0 392 32>;
-+	};
-+};
-+
-+&main_navss {
-+	/delete-node/ main_navss_intr;
-+	/delete-node/ main_navss_inta;
-+
-+	main_navss_intr: interrupt-controller1 {
-+		compatible = "ti,sci-intr";
-+		ti,intr-trigger-type = <4>;
-+		interrupt-controller;
-+		interrupt-parent = <&gic500>;
-+		#interrupt-cells = <1>;
-+		ti,sci = <&dmsc>;
-+		ti,sci-dev-id = <182>;
-+		ti,interrupt-ranges = <0 64 64>,
-+				      <64 448 64>;
-+	};
-+
-+	main_udmass_inta: interrupt-controller@33d00000 {
-+		compatible = "ti,sci-inta";
-+		reg = <0x0 0x33d00000 0x0 0x100000>;
-+		interrupt-controller;
-+		interrupt-parent = <&main_navss_intr>;
-+		#interrupt-cells = <3>;
-+		ti,sci = <&dmsc>;
-+		ti,sci-dev-id = <179>;
-+		ti,interrupt-ranges = <0 0 256>;
-+	};
-+};
-+
-+&mailbox0_cluster0 {
-+	interrupt-parent = <&main_navss_intr>;
-+	interrupts = <436>;
-+};
-+
-+&mailbox0_cluster1 {
-+	interrupt-parent = <&main_navss_intr>;
-+	interrupts = <432>;
-+};
-+
-+&ringacc {
-+	ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
-+};
-+
-+&main_udmap {
-+	ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
-+				<0xd>; /* TX_CHAN */
-+	ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
-+				<0xa>; /* RX_CHAN */
-+	ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
-+};
-+
-+&main_cpts {
-+	interrupts-extended = <&main_navss_intr 391>;
-+	interrupt-names = "cpts";
-+};
-+
-+&main_gpio0 {
-+	interrupt-parent = <&intr_main_gpio>;
-+	interrupts = <192>, <193>, <194>, <195>, <196>, <197>;
-+};
-+
-+&main_gpio1 {
-+		interrupt-parent = <&intr_main_gpio>;
-+		interrupts = <200>, <201>, <202>, <203>, <204>, <205>;
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
-index 8172f1b88038..7bb3dfbe924b 100644
---- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
-+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
-@@ -388,7 +388,7 @@
- 			ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
- 		};
- 
--		cpts@310d0000 {
-+		main_cpts: cpts@310d0000 {
- 			compatible = "ti,am65-cpts";
- 			reg = <0x0 0x310d0000 0x0 0x400>;
- 			reg-names = "cpts";
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu-abi3_x.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu-abi3_x.dtsi
-new file mode 100644
-index 000000000000..963ea000078d
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu-abi3_x.dtsi
-@@ -0,0 +1,18 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Device Tree Source for AM6 SoC Family MCU Domain peripherals
-+ *
-+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
-+ */
-+
-+&mcu_ringacc {
-+	ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
-+};
-+
-+&mcu_udmap {
-+	ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */
-+				<0xd>; /* TX_CHAN */
-+	ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */
-+				<0xa>; /* RX_CHAN */
-+	ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup-abi3_x.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup-abi3_x.dtsi
-new file mode 100644
-index 000000000000..04e5221d65bb
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup-abi3_x.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
-+ *
-+ * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
-+ */
-+
-+&cbass_wakeup {
-+	/delete-node/ wkup_intr;
-+	intr_wkup_gpio: interrupt-controller2 {
-+		compatible = "ti,sci-intr";
-+		ti,intr-trigger-type = <1>;
-+		interrupt-controller;
-+		interrupt-parent = <&gic500>;
-+		#interrupt-cells = <1>;
-+		ti,sci = <&dmsc>;
-+		ti,sci-dev-id = <156>;
-+		ti,interrupt-ranges = <0 712 16>;
-+	};
-+};
-+
-+&wkup_gpio0 {
-+	interrupt-parent = <&intr_wkup_gpio>;
-+	interrupts = <60>, <61>, <62>, <63>;
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board-abi3_x.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board-abi3_x.dts
-new file mode 100644
-index 000000000000..436d8ba877ad
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board-abi3_x.dts
-@@ -0,0 +1,16 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
-+ */
-+
-+/dts-v1/;
-+
-+#include "k3-am654-base-board.dts"
-+#include "k3-am65-main-abi3_x.dtsi"
-+#include "k3-am65-mcu-abi3_x.dtsi"
-+#include "k3-am65-wakeup-abi3_x.dtsi"
-+
-+/ {
-+	compatible =  "ti,am654-evm", "ti,am654";
-+	model = "Texas Instruments AM654 Base Board using sysfw ABI 3.x";
-+};
--- 
-2.31.1
-

board/PSG/iot2050/files/0008-iot2050-add-iot2050-platform-support.patch

@@ -1,1115 +0,0 @@
-From 81db1f21530d256a248a0bc51a71ab5bdf819fdf Mon Sep 17 00:00:00 2001
-From: Le Jin <le.jin@siemens.com>
-Date: Mon, 18 Nov 2019 17:58:08 +0800
-Subject: [PATCH 08/26] iot2050: add iot2050 platform support
-
-Add support for two iot2050 variants, BASIC and ADVANCED.
-Also add support for fixed gpio number naming.
-
-Signed-off-by: le.jin <le.jin@siemens.com>
----
- arch/arm64/boot/dts/ti/Makefile               |   5 +
- .../boot/dts/ti/k3-am65-iot2050-oldfw.dtsi    |  20 +
- arch/arm64/boot/dts/ti/k3-am65-iot2050.dtsi   | 795 ++++++++++++++++++
- .../dts/ti/k3-am6528-iot2050-basic-oldfw.dts  |  24 +
- .../boot/dts/ti/k3-am6528-iot2050-basic.dts   |  12 +
- .../boot/dts/ti/k3-am6528-iot2050-basic.dtsi  |  47 ++
- .../ti/k3-am6548-iot2050-advanced-oldfw.dts   |  10 +
- .../dts/ti/k3-am6548-iot2050-advanced.dts     |  12 +
- .../dts/ti/k3-am6548-iot2050-advanced.dtsi    |  53 ++
- drivers/gpio/gpio-davinci.c                   |  10 +
- drivers/tty/serial/8250/8250_port.c           |   5 +-
- 11 files changed, 991 insertions(+), 2 deletions(-)
- create mode 100644 arch/arm64/boot/dts/ti/k3-am65-iot2050-oldfw.dtsi
- create mode 100644 arch/arm64/boot/dts/ti/k3-am65-iot2050.dtsi
- create mode 100644 arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-oldfw.dts
- create mode 100644 arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
- create mode 100644 arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dtsi
- create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-oldfw.dts
- create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
- create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dtsi
-
-diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
-index b952d3e730d6..3f6fc2f8445c 100644
---- a/arch/arm64/boot/dts/ti/Makefile
-+++ b/arch/arm64/boot/dts/ti/Makefile
-@@ -22,6 +22,11 @@ dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb \
- 	k3-am654-base-board-jailhouse.dtbo \
- 	k3-am654-evm-prupwm.dtbo
- 
-+dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am6528-iot2050-basic-oldfw.dtb
-+dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am6528-iot2050-basic.dtb
-+dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am6548-iot2050-advanced-oldfw.dtb
-+dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am6548-iot2050-advanced.dtb
-+
- dtb-$(CONFIG_ARCH_K3_J721E_SOC) += k3-j721e-common-proc-board.dtb \
- 				   k3-j721e-proc-board-tps65917.dtb \
- 				   k3-j721e-common-proc-board-infotainment.dtbo \
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-oldfw.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-oldfw.dtsi
-new file mode 100644
-index 000000000000..93b53d63ef60
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-oldfw.dtsi
-@@ -0,0 +1,20 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/*
-+ * Swap clock TISCI clock IDs between sdhci0 and sdhci1 to work
-+ * around an issue in System Firmware 2019.12a (and earlier) known
-+ * as SYSFW-3179.
-+ */
-+
-+&sdhci0 {
-+	clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
-+	assigned-clocks = <&k3_clks 48 1>;
-+	assigned-clock-rates = <142860000>;
-+};
-+
-+&sdhci1 {
-+	clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050.dtsi
-new file mode 100644
-index 000000000000..c32c75e80e85
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050.dtsi
-@@ -0,0 +1,795 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/net/ti-dp83867.h>
-+#include <dt-bindings/phy/phy.h>
-+#include "k3-am654.dtsi"
-+
-+/ {
-+	aliases {
-+		ethernet1 = &pruss0_emac0;
-+		ethernet2 = &pruss0_emac1;
-+		gpio0 = &main_gpio0;
-+		gpio96 = &main_gpio1;
-+		gpio186 = &wkup_gpio0;
-+		spi0 = &mcu_spi0;
-+	};
-+
-+	chosen {
-+		stdout-path = "serial3:115200n8";
-+		bootargs = "earlycon=ns16550a,mmio32,0x02800000";
-+	};
-+
-+	reserved-memory {
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+
-+		secure_ddr: secure_ddr@9e800000 {
-+			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
-+			alignment = <0x1000>;
-+			no-map;
-+		};
-+
-+		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
-+			compatible = "shared-dma-pool";
-+			reg = <0 0xa0000000 0 0x100000>;
-+			no-map;
-+		};
-+
-+		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
-+			compatible = "shared-dma-pool";
-+			reg = <0 0xa0100000 0 0xf00000>;
-+			no-map;
-+		};
-+
-+		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
-+			compatible = "shared-dma-pool";
-+			reg = <0 0xa1000000 0 0x100000>;
-+			no-map;
-+		};
-+
-+		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
-+			compatible = "shared-dma-pool";
-+			reg = <0 0xa1100000 0 0xf00000>;
-+			no-map;
-+		};
-+
-+		rtos_ipc_memory_region: ipc-memories@a2000000 {
-+			reg = <0x00 0xa2000000 0x00 0x00200000>;
-+			alignment = <0x1000>;
-+			no-map;
-+		};
-+	};
-+
-+	gpio_leds {
-+		compatible = "gpio-leds";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&leds_pins_default>;
-+
-+		status-led-red {
-+			gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
-+			panic-indicator;
-+			linux,default-trigger = "gpio";
-+		};
-+
-+		status-led-green {
-+			gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
-+			panic-indicator-off;
-+			linux,default-trigger = "gpio";
-+		};
-+
-+		user-led1-red {
-+			gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "gpio";
-+		};
-+
-+		user-led1-green {
-+			gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "gpio";
-+		};
-+
-+		user-led2-red {
-+			gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "gpio";
-+		};
-+
-+		user-led2-green {
-+			gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
-+			linux,default-trigger = "gpio";
-+		};
-+	};
-+
-+	dp_refclk: clock {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <19200000>;
-+	};
-+
-+	/* Dual Ethernet application node on PRU-ICSSG0 */
-+	pruss0_eth {
-+		compatible = "ti,am654-icssg-prueth";
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&icssg0_rgmii_pins_default>;
-+		sram = <&msmc_ram>;
-+		interrupt-parent = <&main_udmass_inta>;
-+
-+		prus = <&pru0_0>, <&rtu0_0>, <&pru0_1>, <&rtu0_1>;
-+		firmware-name = "ti-pruss/am65x-pru0-prueth-fw.elf",
-+				"ti-pruss/am65x-rtu0-prueth-fw.elf",
-+				"ti-pruss/am65x-pru1-prueth-fw.elf",
-+				"ti-pruss/am65x-rtu1-prueth-fw.elf";
-+		mii-g-rt = <&icssg0_mii_g_rt>;
-+		mii-rt = <&icssg0_mii_rt>;
-+		dma-coherent;
-+		dmas = <&main_udmap &icssg0 0 UDMA_DIR_TX>, /* egress slice 0 */
-+			<&main_udmap &icssg0 1 UDMA_DIR_TX>, /* egress slice 0 */
-+			<&main_udmap &icssg0 2 UDMA_DIR_TX>, /* egress slice 0 */
-+			<&main_udmap &icssg0 3 UDMA_DIR_TX>, /* egress slice 0 */
-+			<&main_udmap &icssg0 4 UDMA_DIR_TX>, /* egress slice 1 */
-+			<&main_udmap &icssg0 5 UDMA_DIR_TX>, /* egress slice 1 */
-+			<&main_udmap &icssg0 6 UDMA_DIR_TX>, /* egress slice 1 */
-+			<&main_udmap &icssg0 7 UDMA_DIR_TX>, /* egress slice 1 */
-+
-+			<&main_udmap &icssg0 0 UDMA_DIR_RX>, /* ingress slice 0 */
-+			<&main_udmap &icssg0 1 UDMA_DIR_RX>, /* ingress slice 1 */
-+			<&main_udmap &icssg0 2 UDMA_DIR_RX>, /* mgmnt rsp slice 0 */
-+			<&main_udmap &icssg0 3 UDMA_DIR_RX>; /* mgmnt rsp slice 1 */
-+		dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
-+				"tx1-0", "tx1-1", "tx1-2", "tx1-3",
-+				"rx0", "rx1",
-+				"rxmgm0", "rxmgm1";
-+
-+		pruss0_emac0: ethernet-mii0 {
-+			phy-handle = <&pruss0_eth0_phy>;
-+			phy-mode = "rgmii-rxid";
-+			syscon-rgmii-delay = <&scm_conf 0x4100>;
-+			iep = <&icssg0_iep0>;
-+			/* Filled in by bootloader */
-+			local-mac-address = [00 00 00 00 00 00];
-+			enable-half-duplex;
-+		};
-+
-+		pruss0_emac1: ethernet-mii1 {
-+			phy-handle = <&pruss0_eth1_phy>;
-+			phy-mode = "rgmii-rxid";
-+			syscon-rgmii-delay = <&scm_conf 0x4104>;
-+			iep = <&icssg0_iep1>;
-+			/* Filled in by bootloader */
-+			local-mac-address = [00 00 00 00 00 00];
-+			enable-half-duplex;
-+		};
-+	};
-+};
-+
-+&wkup_pmx0 {
-+	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
-+			AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
-+		>;
-+	};
-+
-+	mcu_i2c0_pins_default: mcu_i2c0_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT, 0) /* (AD8) MCU_I2C0_SCL */
-+			AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT, 0) /* (AD7) MCU_I2C0_SDA */
-+		>;
-+	};
-+
-+	arduino_i2c_aio_switch_pins_default: arduino_i2c_aio_switch_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)  /* (R2) WKUP_GPIO0_21 */
-+		>;
-+	};
-+
-+	push_button_pins_default: push_button_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
-+		>;
-+	};
-+
-+	arduino_uart_pins_default: arduino_uart_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4)	/* (P4) MCU_UART0_RXD */
-+			AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)/* (P5) MCU_UART0_TXD */
-+		>;
-+	};
-+
-+	arduino_io_d2_to_d3_pins_default: arduino_io_d2_to_d3_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)/* (P1) WKUP_GPIO0_31 */
-+			AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)/* (N3) WKUP_GPIO0_33 */
-+		>;
-+	};
-+
-+	arduino_io_oe_pins_default: arduino_io_oe_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)/* (N4) WKUP_GPIO0_34 */
-+			AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)/* (M2) WKUP_GPIO0_36 */
-+			AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)/* (M3) WKUP_GPIO0_37 */
-+			AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)/* (M4) WKUP_GPIO0_38 */
-+			AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)/* (M1) WKUP_GPIO0_41 */
-+		>;
-+	};
-+
-+	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
-+			AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* (U4) MCU_OSPI0_D0 */
-+			AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* (U5) MCU_OSPI0_D1 */
-+			AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
-+		>;
-+	};
-+
-+	db9_com_mode_pins_default: db9_com_mode_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)  /* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
-+			AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)  /* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
-+			AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)  /* (AC1) WKUP_GPIO0_7, used as uart0 term */
-+			AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)  /* (AC2) WKUP_GPIO0_6, used as uart0 en */
-+		>;
-+	};
-+
-+	leds_pins_default: leds_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)  /* (T2) WKUP_GPIO0_17, used as user led1 red */
-+			AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)  /* (R3) WKUP_GPIO0_22, used as user led1 green */
-+			AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)  /* (R5) WKUP_GPIO0_24, used as status led red */
-+			AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)  /* (R5) WKUP_GPIO0_32, used as status led green */
-+		>;
-+	};
-+
-+	mcu_spi0_pins_default: mcu_spi0_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* (Y1) MCU_SPI0_CLK */
-+			AM65X_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* (Y3) MCU_SPI0_D0 */
-+			AM65X_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (Y2) MCU_SPI0_D1 */
-+			AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (Y4) MCU_SPI0_CS0 */
-+		>;
-+	};
-+
-+	minipcie_pins_default: minipcie_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)  /* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
-+		>;
-+	};
-+};
-+
-+&main_pmx0 {
-+	main_uart1_pins_default: main_uart1_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0174, PIN_INPUT, 6)	/* (AE23) UART1_RXD */
-+			AM65X_IOPAD(0x014c, PIN_OUTPUT, 6)	/* (AD23) UART1_TXD */
-+			AM65X_IOPAD(0x0178, PIN_INPUT, 6)	/* (AD22) UART1_CTSn */
-+			AM65X_IOPAD(0x017c, PIN_OUTPUT, 6)	/* (AC21) UART1_RTSn */
-+		>;
-+	};
-+
-+	main_i2c3_pins_default: main_i2c3_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x01c0, PIN_INPUT, 2) /* (AF13) I2C3_SCL */
-+			AM65X_IOPAD(0x01d4, PIN_INPUT, 2) /* (AG12) I2C3_SDA */
-+		>;
-+	};
-+
-+	main_mmc1_pins_default: main_mmc1_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
-+			AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
-+			AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
-+			AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
-+			AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
-+			AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
-+			AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
-+			AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP, 0) /* (C24) MMC1_SDWP */
-+		>;
-+	};
-+
-+	usb0_pins_default: usb0_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
-+		>;
-+	};
-+
-+	usb1_pins_default: usb1_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
-+		>;
-+	};
-+
-+	arduino_io_d4_to_d9_pins_default: arduino_io_d4_to_d9_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0084, PIN_OUTPUT, 7)/* (AG18) GPIO0_33 */
-+			AM65X_IOPAD(0x008C, PIN_OUTPUT, 7)/* (AF17) GPIO0_35 */
-+			AM65X_IOPAD(0x0098, PIN_OUTPUT, 7)/* (AH16) GPIO0_38 */
-+			AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7)/* (AH15) GPIO0_43 */
-+			AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7)/* (AG15) GPIO0_48 */
-+			AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7)/* (AD15) GPIO0_51 */
-+		>;
-+	};
-+
-+	icssg0_mdio_pins_default: icssg0_mdio_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0294, PIN_INPUT, 0) /* (AE26) PRG0_MDIO0_MDIO */
-+			AM65X_IOPAD(0x0298, PIN_OUTPUT, 0) /* (AE28) PRG0_MDIO0_MDC */
-+		>;
-+	};
-+
-+	icssg0_rgmii_pins_default: icssg0_rgmii_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0244, PIN_INPUT, 2) /* (AB28) PRG0_PRU1_GPO0.PRG0_RGMII2_RD0 */
-+			AM65X_IOPAD(0x0248, PIN_INPUT, 2) /* (AC28) PRG0_PRU1_GPO1.PRG0_RGMII2_RD1 */
-+			AM65X_IOPAD(0x024c, PIN_INPUT, 2) /* (AC27) PRG0_PRU1_GPO2.PRG0_RGMII2_RD2 */
-+			AM65X_IOPAD(0x0250, PIN_INPUT, 2) /* (AB26) PRG0_PRU1_GPO3.PRG0_RGMII2_RD3 */
-+			AM65X_IOPAD(0x0274, PIN_OUTPUT, 2) /* (AC25) PRG0_PRU1_GPO12.PRG0_RGMII2_TD0 */
-+			AM65X_IOPAD(0x0278, PIN_OUTPUT, 2) /* (AD25) PRG0_PRU1_GPO13.PRG0_RGMII2_TD1 */
-+			AM65X_IOPAD(0x027c, PIN_OUTPUT, 2) /* (AD24) PRG0_PRU1_GPO14.PRG0_RGMII2_TD2 */
-+			AM65X_IOPAD(0x0280, PIN_OUTPUT, 2) /* (AE27) PRG0_PRU1_GPO15.PRG0_RGMII2_TD3 */
-+			AM65X_IOPAD(0x0284, PIN_INPUT, 2) /* (AC24) PRG0_PRU1_GPO16.PRG0_RGMII2_TXC */
-+			AM65X_IOPAD(0x0270, PIN_OUTPUT, 2) /* (AB24) PRG0_PRU1_GPO11.PRG0_RGMII2_TX_CTL */
-+			AM65X_IOPAD(0x025c, PIN_INPUT, 2) /* (AB27) PRG0_PRU1_GPO6.PRG0_RGMII2_RXC */
-+			AM65X_IOPAD(0x0254, PIN_INPUT, 2) /* (AA25) PRG0_PRU1_GPO4.PRG0_RGMII2_RX_CTL */
-+
-+			AM65X_IOPAD(0x01f4, PIN_INPUT, 2) /* (V24) PRG0_PRU0_GPO0.PRG0_RGMII1_RD0 */
-+			AM65X_IOPAD(0x01f8, PIN_INPUT, 2) /* (W25) PRG0_PRU0_GPO1.PRG0_RGMII1_RD1 */
-+			AM65X_IOPAD(0x01fc, PIN_INPUT, 2) /* (W24) PRG0_PRU0_GPO2.PRG0_RGMII1_RD2 */
-+			AM65X_IOPAD(0x0200, PIN_INPUT, 2) /* (AA27) PRG0_PRU0_GPO3.PRG0_RGMII1_RD3 */
-+			AM65X_IOPAD(0x0224, PIN_OUTPUT, 2) /* (AD27) PRG0_PRU0_GPO12.PRG0_RGMII1_TD0 */
-+			AM65X_IOPAD(0x0228, PIN_OUTPUT, 2) /* (AC26) PRG0_PRU0_GPO13.PRG0_RGMII1_TD1 */
-+			AM65X_IOPAD(0x022c, PIN_OUTPUT, 2) /* (AD26) PRG0_PRU0_GPO14.PRG0_RGMII1_TD2 */
-+			AM65X_IOPAD(0x0230, PIN_OUTPUT, 2) /* (AA24) PRG0_PRU0_GPO15.PRG0_RGMII1_TD3 */
-+			AM65X_IOPAD(0x0234, PIN_INPUT, 2) /* (AD28) PRG0_PRU0_GPO16.PRG0_RGMII1_TXC */
-+			AM65X_IOPAD(0x0220, PIN_OUTPUT, 2) /* (AB25) PRG0_PRU0_GPO11.PRG0_RGMII1_TX_CTL */
-+			AM65X_IOPAD(0x020c, PIN_INPUT, 2) /* (Y25) PRG0_PRU0_GPO6.PRG0_RGMII1_RXC */
-+			AM65X_IOPAD(0x0204, PIN_INPUT, 2) /* (Y24) PRG0_PRU0_GPO4.PRG0_RGMII1_RX_CTL */
-+		>;
-+	};
-+
-+	dss_vout1_pins_default: dss_vout1_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0000, PIN_OUTPUT, 1)	/* VOUT1_DATA0 */
-+			AM65X_IOPAD(0x0004, PIN_OUTPUT, 1)	/* VOUT1_DATA1 */
-+			AM65X_IOPAD(0x0008, PIN_OUTPUT, 1)	/* VOUT1_DATA2 */
-+			AM65X_IOPAD(0x000c, PIN_OUTPUT, 1)	/* VOUT1_DATA3 */
-+			AM65X_IOPAD(0x0010, PIN_OUTPUT, 1)	/* VOUT1_DATA4 */
-+			AM65X_IOPAD(0x0014, PIN_OUTPUT, 1)	/* VOUT1_DATA5 */
-+			AM65X_IOPAD(0x0018, PIN_OUTPUT, 1)	/* VOUT1_DATA6 */
-+			AM65X_IOPAD(0x001c, PIN_OUTPUT, 1)	/* VOUT1_DATA7 */
-+			AM65X_IOPAD(0x0020, PIN_OUTPUT, 1)	/* VOUT1_DATA8 */
-+			AM65X_IOPAD(0x0024, PIN_OUTPUT, 1)	/* VOUT1_DATA9 */
-+			AM65X_IOPAD(0x0028, PIN_OUTPUT, 1)	/* VOUT1_DATA10 */
-+			AM65X_IOPAD(0x002c, PIN_OUTPUT, 1)	/* VOUT1_DATA11 */
-+			AM65X_IOPAD(0x0030, PIN_OUTPUT, 1)	/* VOUT1_DATA12 */
-+			AM65X_IOPAD(0x0034, PIN_OUTPUT, 1)	/* VOUT1_DATA13 */
-+			AM65X_IOPAD(0x0038, PIN_OUTPUT, 1)	/* VOUT1_DATA14 */
-+			AM65X_IOPAD(0x003c, PIN_OUTPUT, 1)	/* VOUT1_DATA15 */
-+			AM65X_IOPAD(0x0040, PIN_OUTPUT, 1)	/* VOUT1_DATA16 */
-+			AM65X_IOPAD(0x0044, PIN_OUTPUT, 1)	/* VOUT1_DATA17 */
-+			AM65X_IOPAD(0x0048, PIN_OUTPUT, 1)	/* VOUT1_DATA18 */
-+			AM65X_IOPAD(0x004c, PIN_OUTPUT, 1)	/* VOUT1_DATA19 */
-+			AM65X_IOPAD(0x0050, PIN_OUTPUT, 1)	/* VOUT1_DATA20 */
-+			AM65X_IOPAD(0x0054, PIN_OUTPUT, 1)	/* VOUT1_DATA21 */
-+			AM65X_IOPAD(0x0058, PIN_OUTPUT, 1)	/* VOUT1_DATA22 */
-+			AM65X_IOPAD(0x005c, PIN_OUTPUT, 1)	/* VOUT1_DATA23 */
-+			AM65X_IOPAD(0x0060, PIN_OUTPUT, 1)	/* VOUT1_VSYNC */
-+			AM65X_IOPAD(0x0064, PIN_OUTPUT, 1)	/* VOUT1_HSYNC */
-+			AM65X_IOPAD(0x0068, PIN_OUTPUT, 1)	/* VOUT1_PCLK */
-+			AM65X_IOPAD(0x006c, PIN_OUTPUT, 1)	/* VOUT1_DE */
-+		>;
-+	};
-+
-+	dp_pins_default: dp_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0078, PIN_OUTPUT, 7)	/* (AF18) DP rst_n */
-+		>;
-+	};
-+
-+	main_i2c2_pins_default: main_i2c2_pins_default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) I2C2_SCL */
-+			AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) I2C2_SDA */
-+		>;
-+	};
-+};
-+
-+&main_pmx1 {
-+	main_i2c0_pins_default: main-i2c0-pins-default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */
-+			AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */
-+		>;
-+	};
-+
-+	main_i2c1_pins_default: main-i2c1-pins-default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */
-+			AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */
-+		>;
-+	};
-+
-+	ecap0_pins_default: ecap0-pins-default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */
-+		>;
-+	};
-+};
-+
-+&wkup_uart0 {
-+	/* Wakeup UART is used by System firmware */
-+	status = "disabled";
-+};
-+
-+&main_uart1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_uart1_pins_default>;
-+};
-+
-+&main_uart2 {
-+	status = "disabled";
-+};
-+
-+&mcu_uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&arduino_uart_pins_default>;
-+};
-+
-+&main_gpio0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
-+	gpio-line-names =
-+		"main_gpio0-base", "", "", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "", "", "",
-+		"", "", "", "IO4", "", "IO5", "", "", "IO6", "",
-+		"", "", "", "IO7", "", "", "", "", "IO8", "",
-+		"", "IO9", "", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "", "", "", "", "",
-+		"", "", "", "", "", "";
-+};
-+
-+&wkup_gpio0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&arduino_io_d2_to_d3_pins_default
-+				&arduino_i2c_aio_switch_pins_default
-+				&arduino_io_oe_pins_default
-+				&push_button_pins_default
-+				&db9_com_mode_pins_default>;
-+	gpio-line-names =
-+		"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
-+			"UART0-enable", "UART0-terminate", "", "WIFI-disable",
-+		"", "", "", "", "", "", "", "", "", "",
-+		"", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
-+		"IO1", "IO2", "", "IO3", "IO17-direction",
-+			"A5", "IO16-direction", "IO15-direction",
-+			"IO14-direction", "A3",
-+		"", "IO18-direction", "A4", "A2", "A1",
-+			"A0", "", "", "IO13", "IO11",
-+		"IO12", "IO10", "", "", "", "";
-+};
-+
-+&wkup_i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&wkup_i2c0_pins_default>;
-+	clock-frequency = <400000>;
-+};
-+
-+&mcu_i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mcu_i2c0_pins_default>;
-+	clock-frequency = <400000>;
-+
-+	psu: tps62363@60 {
-+		compatible = "ti,tps62363";
-+		reg =  <0x60>;
-+		regulator-name = "tps62363-vout";
-+		regulator-min-microvolt = <500000>;
-+		regulator-max-microvolt = <1500000>;
-+		regulator-boot-on;
-+		/* ti,vsel0-gpio = <&gpio1 16 0>; */
-+		/* ti,vsel1-gpio = <&gpio1 17 0>; */
-+		ti,vsel0-state-high;
-+		ti,vsel1-state-high;
-+		/* ti,enable-pull-down; */
-+		/* ti,enable-force-pwm; */
-+		ti,enable-vout-discharge;
-+	};
-+
-+	/*D4200*/
-+	pcal9535_1: gpio@20 {
-+		compatible = "nxp,pcal9535";
-+		reg = <0x20>;
-+		#gpio-cells = <2>;
-+		gpio-controller;
-+		gpio-line-names =
-+			"A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
-+			"A5-pull", "", "",
-+			"IO14-enable", "IO15-enable", "IO16-enable",
-+			"IO17-enable", "IO18-enable", "IO19-enable", "", "";
-+	};
-+
-+	/*D4201*/
-+	pcal9535_2: gpio@21 {
-+		compatible = "nxp,pcal9535";
-+		reg = <0x21>;
-+		#gpio-cells = <2>;
-+		gpio-controller;
-+		gpio-line-names =
-+			"IO0-direction", "IO1-direction", "IO2-direction",
-+			"IO3-direction", "IO4-direction", "IO5-direction",
-+			"IO6-direction", "IO7-direction",
-+			"IO8-direction", "IO9-direction", "IO10-direction",
-+			"IO11-direction", "IO12-direction", "IO13-direction",
-+			"IO19-direction", "";
-+	};
-+
-+	/*D4202*/
-+	pcal9535_3: gpio@25 {
-+		compatible = "nxp,pcal9535";
-+		reg = <0x25>;
-+		#gpio-cells = <2>;
-+		gpio-controller;
-+		gpio-line-names =
-+			"IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
-+			"IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
-+			"IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
-+			"IO12-pull", "IO13-pull", "", "";
-+	};
-+};
-+
-+&main_i2c0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_i2c0_pins_default>;
-+	clock-frequency = <400000>;
-+
-+	rtc:rtc8564@51 {
-+		compatible = "nxp,pcf8563";
-+		reg = <0x51>;
-+	};
-+
-+	eeprom: eeprom@54 {
-+		compatible = "atmel,24c08";
-+		reg = <0x54>;
-+		pagesize = <16>;
-+	};
-+};
-+
-+&main_i2c1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_i2c1_pins_default>;
-+	clock-frequency = <400000>;
-+};
-+
-+&main_i2c2 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_i2c2_pins_default>;
-+	clock-frequency = <400000>;
-+};
-+
-+&main_i2c3 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_i2c3_pins_default>;
-+	clock-frequency = <400000>;
-+
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	edp-bridge@f {
-+		compatible = "toshiba,tc358867", "toshiba,tc358767";
-+		reg = <0x0f>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&dp_pins_default>;
-+		reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
-+
-+		clock-names = "ref";
-+		clocks = <&dp_refclk>;
-+
-+		toshiba,hpd-pin = <0>;
-+
-+		ports {
-+			#address-cells = <1>;
-+			#size-cells = <0>;
-+
-+			port@1 {
-+				reg = <1>;
-+
-+				bridge_in: endpoint {
-+					remote-endpoint = <&dpi_out>;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&mcu_cpsw {
-+	status = "disabled";
-+};
-+
-+&ecap0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&ecap0_pins_default>;
-+};
-+
-+&sdhci1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_mmc1_pins_default>;
-+	ti,driver-strength-ohm = <50>;
-+	disable-wp;
-+};
-+
-+&gpu {
-+	status = "okay";
-+};
-+
-+&dwc3_0 {
-+	status = "okay";
-+};
-+
-+&usb0_phy {
-+	status = "okay";
-+};
-+
-+&usb0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&usb0_pins_default>;
-+	dr_mode = "host";
-+};
-+
-+&dwc3_1 {
-+	status = "okay";
-+};
-+
-+&usb1_phy {
-+	status = "okay";
-+};
-+
-+&usb1 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&usb1_pins_default>;
-+	dr_mode = "host";
-+};
-+
-+&mcu_spi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mcu_spi0_pins_default>;
-+
-+	#address-cells = <1>;
-+	#size-cells= <0>;
-+	ti,pindir-d0-out-d1-in = <1>;
-+
-+	spidev@0x00 {
-+		compatible = "rohm,dh2228fv";
-+		spi-max-frequency = <20000000>;
-+		reg = <0>;
-+	};
-+};
-+
-+&tscadc0 {
-+	status = "disabled";
-+};
-+
-+&tscadc1 {
-+	adc {
-+		ti,adc-channels = <0 1 2 3 4 5>;
-+	};
-+};
-+
-+&mcu_r5fss0_core0 {
-+	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
-+			<&mcu_r5fss0_core0_memory_region>;
-+};
-+
-+&mcu_r5fss0_core1 {
-+	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
-+			<&mcu_r5fss0_core1_memory_region>;
-+};
-+
-+&ospi0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
-+
-+	flash@0{
-+		compatible = "jedec,spi-nor";
-+		reg = <0x0>;
-+		spi-tx-bus-width = <1>;
-+		spi-rx-bus-width = <1>;
-+		spi-max-frequency = <50000000>;
-+		cdns,tshsl-ns = <60>;
-+		cdns,tsd2d-ns = <60>;
-+		cdns,tchsh-ns = <60>;
-+		cdns,tslch-ns = <60>;
-+		cdns,read-delay = <2>;
-+		#address-cells = <1>;
-+		#size-cells = <1>;
-+	};
-+};
-+
-+&dss {
-+	status = "okay";
-+
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&dss_vout1_pins_default>;
-+
-+	assigned-clocks = <&k3_clks 67 2>;
-+	assigned-clock-parents = <&k3_clks 67 5>;
-+};
-+
-+&dss_ports {
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+	port@1 {
-+		reg = <1>;
-+
-+		dpi_out: endpoint {
-+			remote-endpoint = <&bridge_in>;
-+		};
-+	};
-+};
-+
-+&icssg0_mdio {
-+	status = "okay";
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&icssg0_mdio_pins_default>;
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	pruss0_eth0_phy: ethernet-phy@0 {
-+		reg = <0>;
-+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-+	};
-+
-+	pruss0_eth1_phy: ethernet-phy@1 {
-+		reg = <1>;
-+		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
-+		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
-+	};
-+};
-+
-+&serdes1 {
-+	status = "okay";
-+};
-+
-+&pcie1_rc {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&minipcie_pins_default>;
-+
-+	phys = <&serdes1 PHY_TYPE_PCIE 0>;
-+	phy-names = "pcie-phy0";
-+	reset-gpio = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
-+	status = "okay";
-+};
-+
-+/* Disable crypto and eip76d_trng temporarily, because the HS system firmware has taken them up */
-+&crypto {
-+	status = "disabled";
-+};
-+
-+&eip76d_trng {
-+	status = "disabled";
-+};
-+
-+/*
-+ * Workaround for UART issues:
-+ * DMA for UARTs does not work with TI kernel but is enabled already in the
-+ * downstream DTS.
-+ */
-+&main_uart0 {
-+	/delete-property/ dmas;
-+	/delete-property/ dma-names;
-+};
-+
-+&main_uart1 {
-+	/delete-property/ dmas;
-+	/delete-property/ dma-names;
-+};
-+
-+&mcu_uart0 {
-+	/delete-property/ dmas;
-+	/delete-property/ dma-names;
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-oldfw.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-oldfw.dts
-new file mode 100644
-index 000000000000..28a2ec6ec4ca
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-oldfw.dts
-@@ -0,0 +1,24 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/dts-v1/;
-+
-+#include "k3-am65-iot2050.dtsi"
-+#include "k3-am6528-iot2050-basic.dtsi"
-+#include "k3-am65-iot2050-oldfw.dtsi"
-+
-+/* Compat support for bootloader V01.00.00.1 */
-+
-+&ospi0 {
-+	clocks = <&k3_clks 55 5>;
-+	assigned-clocks = <&k3_clks 55 5>;
-+	assigned-clock-parents = <&k3_clks 55 7>;
-+	power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
-+};
-+
-+&ospi1 {
-+	clocks = <&k3_clks 55 16>;
-+	power-domains = <&k3_pds 55 TI_SCI_PD_EXCLUSIVE>;
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
-new file mode 100644
-index 000000000000..835bd694feb0
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
-@@ -0,0 +1,12 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/dts-v1/;
-+
-+#include "k3-am65-iot2050.dtsi"
-+#include "k3-am6528-iot2050-basic.dtsi"
-+#include "k3-am65-main-abi3_x.dtsi"
-+#include "k3-am65-mcu-abi3_x.dtsi"
-+#include "k3-am65-wakeup-abi3_x.dtsi"
-diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dtsi
-new file mode 100644
-index 000000000000..14d0fa84dd2b
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dtsi
-@@ -0,0 +1,47 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/ {
-+	compatible = "siemens,iot2050-basic", "ti,am654";
-+	model = "SIMATIC IOT2050 Basic";
-+
-+	memory@80000000 {
-+		device_type = "memory";
-+		/* 1G RAM */
-+		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
-+	};
-+
-+	cpus {
-+		cpu-map {
-+			/delete-node/ cluster1;
-+		};
-+		/delete-node/ cpu@100;
-+		/delete-node/ cpu@101;
-+	};
-+};
-+
-+&main_pmx0 {
-+	main_uart0_pins_default: main-uart0-pins-default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x01e4, PIN_INPUT,  0)  /* (AF11) UART0_RXD */
-+			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)  /* (AE11) UART0_TXD */
-+			AM65X_IOPAD(0x01ec, PIN_INPUT,  0)  /* (AG11) UART0_CTSn */
-+			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)  /* (AD11) UART0_RTSn */
-+			AM65X_IOPAD(0x0188, PIN_INPUT,  1)  /* (D25) UART0_DCDn */
-+			AM65X_IOPAD(0x018c, PIN_INPUT,  1)  /* (B26) UART0_DSRn */
-+			AM65X_IOPAD(0x0190, PIN_OUTPUT, 1)  /* (A24) UART0_DTRn */
-+			AM65X_IOPAD(0x0194, PIN_INPUT,  1)  /* (E24) UART0_RIN */
-+		>;
-+	};
-+};
-+
-+&main_uart0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_uart0_pins_default>;
-+};
-+
-+&sdhci0 {
-+	status = "disabled";
-+};
-diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-oldfw.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-oldfw.dts
-new file mode 100644
-index 000000000000..f17cc47e0560
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-oldfw.dts
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/dts-v1/;
-+
-+#include "k3-am65-iot2050.dtsi"
-+#include "k3-am6548-iot2050-advanced.dtsi"
-+#include "k3-am65-iot2050-oldfw.dtsi"
-diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
-new file mode 100644
-index 000000000000..a98c00af983b
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
-@@ -0,0 +1,12 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/dts-v1/;
-+
-+#include "k3-am65-iot2050.dtsi"
-+#include "k3-am6548-iot2050-advanced.dtsi"
-+#include "k3-am65-main-abi3_x.dtsi"
-+#include "k3-am65-mcu-abi3_x.dtsi"
-+#include "k3-am65-wakeup-abi3_x.dtsi"
-diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dtsi
-new file mode 100644
-index 000000000000..498e6cc7fa87
---- /dev/null
-+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dtsi
-@@ -0,0 +1,53 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * (C) Copyright 2018-2020 Siemens AG
-+ */
-+
-+/ {
-+	compatible = "siemens,iot2050-advanced", "ti,am654";
-+	model = "SIMATIC IOT2050 Advanced";
-+
-+	aliases {
-+		mmc0 = &sdhci1;
-+		mmc1 = &sdhci0;
-+	};
-+
-+	memory@80000000 {
-+		device_type = "memory";
-+		/* 2G RAM */
-+		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
-+	};
-+};
-+
-+&main_uart0 {
-+	status = "disabled";
-+};
-+
-+&main_pmx0 {
-+	main_mmc0_pins_default: main-mmc0-pins-default {
-+		pinctrl-single,pins = <
-+			AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)  /* (B25) MMC0_CLK */
-+			AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP,   0)  /* (B27) MMC0_CMD */
-+			AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP,   0)  /* (A26) MMC0_DAT0 */
-+			AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP,   0)  /* (E25) MMC0_DAT1 */
-+			AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP,   0)  /* (C26) MMC0_DAT2 */
-+			AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP,   0)  /* (A25) MMC0_DAT3 */
-+			AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP,   0)  /* (E24) MMC0_DAT4 */
-+			AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP,   0)  /* (A24) MMC0_DAT5 */
-+			AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP,   0)  /* (B26) MMC0_DAT6 */
-+			AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP,   0)  /* (D25) MMC0_DAT7 */
-+			AM65X_IOPAD(0x01B8, PIN_OUTPUT_PULLUP,  7)  /* (B23) MMC0_SDWP */
-+			AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP,   0)  /* (A23) MMC0_SDCD */
-+			AM65X_IOPAD(0x01b0, PIN_INPUT,          0)  /* (C25) MMC0_DS */
-+		>;
-+	};
-+};
-+
-+&sdhci0 {
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&main_mmc0_pins_default>;
-+	bus-width = <8>;
-+	non-removable;
-+	ti,driver-strength-ohm = <50>;
-+	disable-wp;
-+};
-diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
-index 994ecd597abe..5030a14e86b5 100644
---- a/drivers/gpio/gpio-davinci.c
-+++ b/drivers/gpio/gpio-davinci.c
-@@ -174,6 +174,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
- 	struct device *dev = &pdev->dev;
- 	struct resource *res;
- 	char label[MAX_LABEL_SIZE];
-+	int gpio_alias_id;
- 
- 	pdata = davinci_gpio_get_pdata(pdev);
- 	if (!pdata) {
-@@ -251,6 +252,15 @@ static int davinci_gpio_probe(struct platform_device *pdev)
- 		chips->chip.request = gpiochip_generic_request;
- 		chips->chip.free = gpiochip_generic_free;
- 	}
-+	/*
-+	 * Traditionally the base is given out in first-come-first-serve order.
-+	 * This might shuffle the numbering of gpios if the probe order changes.
-+	 * So make the base deterministical if the device tree specifies alias
-+	 * ids.
-+	 */
-+	gpio_alias_id = of_alias_get_id(dev->of_node, "gpio");
-+	if (gpio_alias_id >= 0)
-+		chips->chip.base = gpio_alias_id;
- #endif
- 	spin_lock_init(&chips->lock);
- 	bank_base += ngpio;
-diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
-index aa4de6907f77..7019cc4e675d 100644
---- a/drivers/tty/serial/8250/8250_port.c
-+++ b/drivers/tty/serial/8250/8250_port.c
-@@ -1868,8 +1868,9 @@ int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
- 	spin_lock_irqsave(&port->lock, flags);
- 
- 	status = serial_port_in(port, UART_LSR);
--
--	if (status & (UART_LSR_DR | UART_LSR_BI)) {
-+	/* '&& iir & UART_IIR_RDI UART_IIR_RDI' will affect hardware flow control */
-+	if (status & (UART_LSR_DR | UART_LSR_BI) &&
-+		iir & UART_IIR_RDI) {
- 		if (!up->dma || handle_rx_dma(up, iir))
- 			status = serial8250_rx_chars(up, status);
- 	}
--- 
-2.31.1
-

board/PSG/iot2050/files/0009-Add-support-for-U9300C-TD-LTE-module.patch

@@ -1,36 +0,0 @@
-From a12e96d0e68acb97c446431277ab0d14001543de Mon Sep 17 00:00:00 2001
-From: Su Bao Cheng <baocheng.su@siemens.com>
-Date: Tue, 23 Apr 2019 10:07:17 +0800
-Subject: [PATCH 09/26] Add support for U9300C TD-LTE module
-
-Author: Gao Nian  <nian.gao@siemens.com>
-Signed-off-by: Su Bao Cheng <baocheng.su@siemens.com>
----
- drivers/usb/serial/option.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
-index 2905274e3626..72d30e29c4d1 100644
---- a/drivers/usb/serial/option.c
-+++ b/drivers/usb/serial/option.c
-@@ -393,6 +393,9 @@ static void option_instat_callback(struct urb *urb);
- /* iBall 3.5G connect wireless modem */
- #define IBALL_3_5G_CONNECT			0x9605
- 
-+/* LONGSUNG U9300C TD-LTE wireless modem */
-+#define LONGSUNG_U9300C   0x9b3c
-+
- /* Zoom */
- #define ZOOM_PRODUCT_4597			0x9607
- 
-@@ -1826,6 +1829,7 @@ static const struct usb_device_id option_ids[] = {
- 	  .driver_info = RSVD(4) },
- 	{ USB_DEVICE(LONGCHEER_VENDOR_ID, ZOOM_PRODUCT_4597) },
- 	{ USB_DEVICE(LONGCHEER_VENDOR_ID, IBALL_3_5G_CONNECT) },
-+	{ USB_DEVICE(LONGCHEER_VENDOR_ID, LONGSUNG_U9300C) },
- 	{ USB_DEVICE(HAIER_VENDOR_ID, HAIER_PRODUCT_CE100) },
- 	{ USB_DEVICE_AND_INTERFACE_INFO(HAIER_VENDOR_ID, HAIER_PRODUCT_CE81B, 0xff, 0xff, 0xff) },
- 	/* Pirelli  */
--- 
-2.31.1
-

board/PSG/iot2050/files/0010-feat-Add-CP210x-driver-support-to-software-flow-cont.patch

@@ -1,190 +0,0 @@
-From 458e2b9abf0d49cb7f7dc605e7d6e8ce6102aaba Mon Sep 17 00:00:00 2001
-From: Su Bao Cheng <baocheng.su@siemens.com>
-Date: Mon, 15 Jul 2019 15:46:09 +0800
-Subject: [PATCH 10/26] feat: Add CP210x driver support to software flow
- control
-
-Signed-off-by: Wang Sheng Long <shenglong.wang.ext@siemens.com>
----
- drivers/usb/serial/cp210x.c | 126 ++++++++++++++++++++++++++++++++++--
- 1 file changed, 121 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
-index 7ae121567098..7815062ed980 100644
---- a/drivers/usb/serial/cp210x.c
-+++ b/drivers/usb/serial/cp210x.c
-@@ -381,6 +381,10 @@ static struct usb_serial_driver * const serial_drivers[] = {
- #define CP210X_PARTNUM_CP2102N_QFN20	0x22
- #define CP210X_PARTNUM_UNKNOWN	0xFF
- 
-+/*vstart and vstop define*/
-+#define CP210X_VSTART  0x11
-+#define CP210X_VSTOP   0x13
-+
- /* CP210X_GET_COMM_STATUS returns these 0x13 bytes */
- struct cp210x_comm_status {
- 	__le32   ulErrors;
-@@ -392,6 +396,16 @@ struct cp210x_comm_status {
- 	u8       bReserved;
- } __packed;
- 
-+/* Characrters Respones 6 bytes*/
-+struct cp210x_chars_respones{
-+	u8       bEofchar;
-+	u8       bErrochar;
-+	u8       bBreakchar;
-+	u8       bEventchar;
-+	u8       bXonchar;
-+	u8       bXoffchar;
-+} __packed;
-+
- /*
-  * CP210X_PURGE - 16 bits passed in wValue of USB request.
-  * SiLabs app note AN571 gives a strange description of the 4 bits:
-@@ -625,6 +639,52 @@ static int cp210x_read_vendor_block(struct usb_serial *serial, u8 type, u16 val,
- 	return result;
- }
- 
-+/*
-+ *func:  Read and Write Characrters Respones
-+ *       operate Register SET_CHARS/GET_CHATS
-+ */
-+static int cp210x_operate_chars_block(struct usb_serial_port *port, u8 req, u8 type,
-+		void *buf, int bufsize)
-+{
-+	struct usb_serial *serial = port->serial;
-+	struct cp210x_port_private *port_priv = usb_get_serial_port_data(port);
-+	void *dmabuf;
-+	int result;
-+
-+	dmabuf = kmemdup(buf,bufsize, GFP_KERNEL);
-+	if (!dmabuf) {
-+		/*
-+		 * FIXME Some callers don't bother to check for error,
-+		 * at least give them consistent junk until they are fixed
-+		 */
-+		memset(buf, 0, bufsize);
-+		return -ENOMEM;
-+	}
-+
-+	result = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
-+			req, type, 0, port_priv->bInterfaceNumber, dmabuf, bufsize,
-+			USB_CTRL_SET_TIMEOUT);
-+	if (result == bufsize) {
-+		memcpy(buf, dmabuf, bufsize);
-+		result = 0;
-+	} else {
-+		dev_err(&port->dev, "failed get req 0x%x size %d status: %d\n",
-+				req, bufsize, result);
-+		if (result >= 0)
-+			result = -EIO;
-+
-+		/*
-+		 * FIXME Some callers don't bother to check for error,
-+		 * at least give them consistent junk until they are fixed
-+		 */
-+		memset(buf, 0, bufsize);
-+	}
-+
-+	kfree(dmabuf);
-+
-+	return result;
-+}
-+
- /*
-  * Writes any 16-bit CP210X_ register (req) whose value is passed
-  * entirely in the wValue field of the USB request.
-@@ -1135,11 +1195,18 @@ static void cp210x_set_termios(struct tty_struct *tty,
- 		struct usb_serial_port *port, struct ktermios *old_termios)
- {
- 	struct device *dev = &port->dev;
--	unsigned int cflag, old_cflag;
-+	struct usb_serial *serial = port->serial;
-+	struct cp210x_chars_respones *CharsRes = NULL;
-+	struct cp210x_flow_ctl flow_ctl;
-+	unsigned int cflag, old_cflag, iflag;
- 	u16 bits;
-+	int result;
-+	u32 ctl_hs;
-+	u32 flow_repl;
- 
- 	cflag = tty->termios.c_cflag;
- 	old_cflag = old_termios->c_cflag;
-+	iflag = tty->termios.c_iflag;
- 
- 	if (tty->termios.c_ospeed != old_termios->c_ospeed)
- 		cp210x_change_speed(tty, port, old_termios);
-@@ -1213,10 +1280,6 @@ static void cp210x_set_termios(struct tty_struct *tty,
- 	}
- 
- 	if ((cflag & CRTSCTS) != (old_cflag & CRTSCTS)) {
--		struct cp210x_flow_ctl flow_ctl;
--		u32 ctl_hs;
--		u32 flow_repl;
--
- 		cp210x_read_reg_block(port, CP210X_GET_FLOW, &flow_ctl,
- 				sizeof(flow_ctl));
- 		ctl_hs = le32_to_cpu(flow_ctl.ulControlHandshake);
-@@ -1253,6 +1316,59 @@ static void cp210x_set_termios(struct tty_struct *tty,
- 				sizeof(flow_ctl));
- 	}
- 
-+	/* Set Software  Flow  Control
-+	 * Xon/Xoff code
-+	 * Check the IXOFF/IXON status in the iflag component of the
-+	 * termios structure.
-+	 *
-+	 */
-+	if  ((iflag & IXOFF) || (iflag & IXON)) {
-+		/*set vstart/vstop chars */
-+		CharsRes = kmalloc(sizeof(*CharsRes), GFP_KERNEL);
-+		if (!CharsRes) {
-+			dev_err(dev, "Characrters Respones kmalloc failed "
-+					"xon/xoff software flow control\n");
-+			return;
-+		}
-+		result = cp210x_operate_chars_block(port, CP210X_GET_CHARS,
-+					  REQTYPE_DEVICE_TO_HOST, CharsRes, sizeof(*CharsRes));
-+		dev_dbg(dev, "%s -  bXonchar=0x%x   bXoffchar=0x%x   \n",
-+				__func__, CharsRes->bXonchar ,CharsRes->bXoffchar);
-+		if (result < 0){
-+			kfree(CharsRes);
-+			dev_err(dev, "Read Characrters Respones  failed "
-+					"xon/xoff software flow control\n");
-+			return;
-+		}
-+		CharsRes->bXonchar  = CP210X_VSTART;
-+		CharsRes->bXoffchar = CP210X_VSTOP;
-+		result = cp210x_operate_chars_block(port, CP210X_SET_CHARS,
-+					 REQTYPE_HOST_TO_INTERFACE, CharsRes, sizeof(*CharsRes));
-+		if (result < 0){
-+			kfree(CharsRes);
-+			dev_err(dev, "Write Characrters Respones  failed"
-+					"xon/xoff software flow control\n");
-+			return;
-+		}
-+		kfree(CharsRes);
-+		/*Set  Rx/Tx Flow Contrl  Flag in ulFlowReplace*/
-+		cp210x_read_reg_block(port, CP210X_GET_FLOW, &flow_ctl,sizeof(flow_ctl));
-+		flow_repl = le32_to_cpu(flow_ctl.ulFlowReplace);
-+		dev_dbg(dev, "%s - read ulControlHandshake=0x%08x, ulFlowReplace=0x%08x\n",
-+				__func__, ctl_hs, flow_repl);
-+		if (iflag & IXOFF)
-+			flow_repl |= CP210X_SERIAL_AUTO_RECEIVE;
-+		else
-+			flow_repl &= ~CP210X_SERIAL_AUTO_RECEIVE;
-+
-+		if (iflag & IXON)
-+			flow_repl |= CP210X_SERIAL_AUTO_TRANSMIT;
-+		else
-+			flow_repl &= ~CP210X_SERIAL_AUTO_TRANSMIT;
-+
-+		flow_ctl.ulFlowReplace = cpu_to_le32(flow_repl);
-+		cp210x_write_reg_block(port, CP210X_SET_FLOW, &flow_ctl,sizeof(flow_ctl));
-+       }
- }
- 
- static int cp210x_tiocmset(struct tty_struct *tty,
--- 
-2.31.1
-

board/PSG/iot2050/files/0011-fix-disable-usb-lpm-to-fix-usb-device-reset.patch

@@ -1,25 +0,0 @@
-From d2a2b8bb376833065d4e2a2e4cb92f15d7404603 Mon Sep 17 00:00:00 2001
-From: Sheng Long Wang <shenglong.wang.ext@siemens.com>
-Date: Tue, 13 Aug 2019 09:30:38 +0800
-Subject: [PATCH 11/26] fix: disable usb lpm to fix usb device reset
-
----
- drivers/usb/core/hub.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
-index b33ec768404b..4fa95d89bfaf 100644
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -4434,7 +4434,7 @@ static void hub_set_initial_usb2_lpm_policy(struct usb_device *udev)
- 	struct usb_hub *hub = usb_hub_to_struct_hub(udev->parent);
- 	int connect_type = USB_PORT_CONNECT_TYPE_UNKNOWN;
- 
--	if (!udev->usb2_hw_lpm_capable || !udev->bos)
-+	//if (!udev->usb2_hw_lpm_capable || !udev->bos)
- 		return;
- 
- 	if (hub)
--- 
-2.31.1
-

board/PSG/iot2050/files/0012-Fix-DP-maybe-not-display-problem.patch

@@ -1,373 +0,0 @@
-From b56e9ca0e2c1adcd339f63e5c77d08bee2eaf3e2 Mon Sep 17 00:00:00 2001
-From: Sheng Long Wang <shenglong.wang.ext@siemens.com>
-Date: Tue, 13 Aug 2019 10:27:44 +0800
-Subject: [PATCH 12/26] Fix: DP maybe not display problem.
-
-Three reasons:
-	1. No entry link training phase
-	2. In Link training phase but link training failed
-	3. max_tu_symbol value Calculate's way erro
-
-For 1.	Modifying reducing polling cycle and it can solve it.
-
-For 2.	link training failed because of the interlane alignment
-	flag is missing during link training(hotpulg maybe
-	also have this problem).In the DP specification,
-	the receiver may defer setting INTERLANE_ALIGN_DONE bit
-	until the receiver may defer setting INTERLANE_ALIGN_DONE
-	bit.And make it optimize is completed.
-	So,try to repeat link training to solve this problem.
-
-For 3.  max_tu_symbol was programmed to TU_SIZE_RECOMMENDED - 1,
-	which is not what the spec says,It may cause some
-	DP-to-VGA apdaters not dispaly.So,Calculate the value as
-	recommended in the spec.
-	This fixes artifacts in some videomodes (e.g.1024x768@60
-	on 2-lanes & 1.62Gbps was pretty bad for me).
-
-Signed-off-by: Sheng Long Wang <shenglong.wang.ext@siemens.com>
----
- drivers/gpu/drm/bridge/tc358767.c  | 283 +++++++++++++++--------------
- drivers/gpu/drm/drm_probe_helper.c |   2 +-
- 2 files changed, 146 insertions(+), 139 deletions(-)
-
-diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
-index 1c2f0cc926c0..262a10b190cb 100644
---- a/drivers/gpu/drm/bridge/tc358767.c
-+++ b/drivers/gpu/drm/bridge/tc358767.c
-@@ -695,7 +695,6 @@ static int tc_set_video_mode(struct tc_data *tc,
- 	 *              (output active video bandwidth in bytes))
- 	 * Must be less than tu_size.
- 	 */
--
- 	in_bw = mode->clock * bits_per_pixel / 8;
- 	out_bw = tc->link.base.num_lanes * tc->link.base.rate;
- 	max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw);
-@@ -800,166 +799,174 @@ static int tc_main_link_enable(struct tc_data *tc)
- 	int ret;
- 	u8 tmp[8];
- 	u32 error;
-+	int retry;
- 
- 	dev_dbg(tc->dev, "link enable\n");
-+	for (retry = 0; retry < 10; retry++)
-+	{
- 
--	tc_write(DP0CTL, 0);
-+		tc_write(DP0CTL, 0);
- 
--	tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
--	/* SSCG and BW27 on DP1 must be set to the same as on DP0 */
--	tc_write(DP1_SRCCTRL,
--		 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
--		 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
-+		tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
-+		/* SSCG and BW27 on DP1 must be set to the same as on DP0 */
-+		tc_write(DP1_SRCCTRL,
-+			 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
-+			 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
- 
--	rate = clk_get_rate(tc->refclk);
--	switch (rate) {
--	case 38400000:
--		value = REF_FREQ_38M4;
--		break;
--	case 26000000:
--		value = REF_FREQ_26M;
--		break;
--	case 19200000:
--		value = REF_FREQ_19M2;
--		break;
--	case 13000000:
--		value = REF_FREQ_13M;
--		break;
--	default:
--		return -EINVAL;
--	}
--	value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
--	tc_write(SYS_PLLPARAM, value);
--
--	/* Setup Main Link */
--	dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
--	if (tc->link.base.num_lanes == 2)
--		dp_phy_ctrl |= PHY_2LANE;
--	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
--
--	/* PLL setup */
--	tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
--	tc_wait_pll_lock(tc);
--
--	tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
--	tc_wait_pll_lock(tc);
--
--	/* Reset/Enable Main Links */
--	dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
--	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
--	usleep_range(100, 200);
--	dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
--	tc_write(DP_PHY_CTRL, dp_phy_ctrl);
--
--	timeout = 1000;
--	do {
--		tc_read(DP_PHY_CTRL, &value);
--		udelay(1);
--	} while ((!(value & PHY_RDY)) && (--timeout));
--
--	if (timeout == 0) {
--		dev_err(dev, "timeout waiting for phy become ready");
--		return -ETIMEDOUT;
--	}
--
--	/* Set misc: 8 bits per color */
--	ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
--	if (ret)
--		goto err;
-+		rate = clk_get_rate(tc->refclk);
-+		switch (rate) {
-+		case 38400000:
-+			value = REF_FREQ_38M4;
-+			break;
-+		case 26000000:
-+			value = REF_FREQ_26M;
-+			break;
-+		case 19200000:
-+			value = REF_FREQ_19M2;
-+			break;
-+		case 13000000:
-+			value = REF_FREQ_13M;
-+			break;
-+		default:
-+			return -EINVAL;
-+		}
-+		value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
-+		tc_write(SYS_PLLPARAM, value);
-+
-+		/* Setup Main Link */
-+		dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
-+		if (tc->link.base.num_lanes == 2)
-+			dp_phy_ctrl |= PHY_2LANE;
-+		tc_write(DP_PHY_CTRL, dp_phy_ctrl);
-+
-+		/* PLL setup */
-+		tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
-+		tc_wait_pll_lock(tc);
-+
-+		tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
-+		tc_wait_pll_lock(tc);
-+
-+		/* Reset/Enable Main Links */
-+		dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
-+		tc_write(DP_PHY_CTRL, dp_phy_ctrl);
-+		usleep_range(100, 200);
-+		dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
-+		tc_write(DP_PHY_CTRL, dp_phy_ctrl);
-+
-+		timeout = 1000;
-+		do {
-+			tc_read(DP_PHY_CTRL, &value);
-+			udelay(1);
-+		} while ((!(value & PHY_RDY)) && (--timeout));
-+
-+		if (timeout == 0) {
-+			dev_err(dev, "timeout waiting for phy become ready");
-+			return -ETIMEDOUT;
-+		}
- 
--	/*
--	 * ASSR mode
--	 * on TC358767 side ASSR configured through strap pin
--	 * seems there is no way to change this setting from SW
--	 *
--	 * check is tc configured for same mode
--	 */
--	if (tc->assr != tc->link.assr) {
--		dev_dbg(dev, "Trying to set display to ASSR: %d\n",
--			tc->assr);
--		/* try to set ASSR on display side */
--		tmp[0] = tc->assr;
--		ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
--		if (ret < 0)
--			goto err_dpcd_read;
--		/* read back */
--		ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
--		if (ret < 0)
--			goto err_dpcd_read;
-+		/* Set misc: 8 bits per color */
-+		ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
-+		if (ret)
-+			goto err;
- 
--		if (tmp[0] != tc->assr) {
--			dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
--				 tc->assr);
--			/* trying with disabled scrambler */
--			tc->link.scrambler_dis = true;
-+		/*
-+		 * ASSR mode
-+		 * on TC358767 side ASSR configured through strap pin
-+		 * seems there is no way to change this setting from SW
-+		 *
-+		 * check is tc configured for same mode
-+		 */
-+		if (tc->assr != tc->link.assr) {
-+			dev_dbg(dev, "Trying to set display to ASSR: %d\n",
-+				tc->assr);
-+			/* try to set ASSR on display side */
-+			tmp[0] = tc->assr;
-+			ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
-+			if (ret < 0)
-+				goto err_dpcd_read;
-+			/* read back */
-+			ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
-+			if (ret < 0)
-+				goto err_dpcd_read;
-+
-+			if (tmp[0] != tc->assr) {
-+				dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
-+					 tc->assr);
-+				/* trying with disabled scrambler */
-+				tc->link.scrambler_dis = true;
-+			}
- 		}
--	}
- 
--	/* Setup Link & DPRx Config for Training */
--	ret = drm_dp_link_configure(aux, &tc->link.base);
--	if (ret < 0)
--		goto err_dpcd_write;
-+		/* Setup Link & DPRx Config for Training */
-+		ret = drm_dp_link_configure(aux, &tc->link.base);
-+		if (ret < 0)
-+			goto err_dpcd_write;
- 
--	/* DOWNSPREAD_CTRL */
--	tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
--	/* MAIN_LINK_CHANNEL_CODING_SET */
--	tmp[1] =  DP_SET_ANSI_8B10B;
--	ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
--	if (ret < 0)
--		goto err_dpcd_write;
-+		/* DOWNSPREAD_CTRL */
-+		tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
-+		/* MAIN_LINK_CHANNEL_CODING_SET */
-+		tmp[1] =  DP_SET_ANSI_8B10B;
-+		ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
-+		if (ret < 0)
-+			goto err_dpcd_write;
- 
--	// Reset voltage-swing & pre-emphasis
--	tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0;
--	ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
--	if (ret < 0)
--		goto err_dpcd_write;
-+		// Reset voltage-swing & pre-emphasis
-+		tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0;
-+		ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2);
-+		if (ret < 0)
-+			goto err_dpcd_write;
- 
--	/* LINK TRAINING PATTERN 1 */
-+		/* LINK TRAINING PATTERN 1 */
- 
--	/* Set DPCD 0x102 for Training Pattern 1 */
--	tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
-+		/* Set DPCD 0x102 for Training Pattern 1 */
-+		tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
- 
--	tc_write(DP0_LTLOOPCTRL,
--		 (15 << 28) |	/* Defer Iteration Count */
--		 (15 << 24) |	/* Loop Iteration Count */
--		 (0xd << 0));	/* Loop Timer Delay */
-+		tc_write(DP0_LTLOOPCTRL,
-+			 (15 << 28) |	/* Defer Iteration Count */
-+			 (15 << 24) |	/* Loop Iteration Count */
-+			 (0xd << 0));	/* Loop Timer Delay */
- 
--	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_AUTOCORRECT |
--		 DP0_SRCCTRL_TP1);
-+		tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_AUTOCORRECT |
-+			 DP0_SRCCTRL_TP1);
- 
--	/* Enable DP0 to start Link Training */
--	tc_write(DP0CTL,
--		 ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) |
--		 DP_EN);
-+		/* Enable DP0 to start Link Training */
-+		tc_write(DP0CTL,
-+			 ((tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? EF_EN : 0) |
-+			 DP_EN);
- 
--	/* wait */
--	ret = tc_wait_link_training(tc, &error);
--	if (ret)
--		goto err;
-+		/* wait */
-+		ret = tc_wait_link_training(tc, &error);
-+		if (ret)
-+			goto err;
- 
--	if (error) {
--		dev_err(tc->dev, "Link training phase 1 failed: %s\n",
--			training_pattern1_errors[error]);
--		ret = -ENODEV;
--		goto err;
--	}
-+		if (error) {
-+			dev_dbg(tc->dev, "Link training phase 1 failed: %s\n",
-+				training_pattern1_errors[error]);
-+			continue;
-+		}
- 
--	/* LINK TRAINING PATTERN 2 */
-+		/* LINK TRAINING PATTERN 2 */
- 
--	/* Set DPCD 0x102 for Training Pattern 2 */
--	tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2);
-+		/* Set DPCD 0x102 for Training Pattern 2 */
-+		tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2);
- 
--	tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_AUTOCORRECT |
--		 DP0_SRCCTRL_TP2);
-+		tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | DP0_SRCCTRL_AUTOCORRECT |
-+			 DP0_SRCCTRL_TP2);
- 
--	/* wait */
--	ret = tc_wait_link_training(tc, &error);
--	if (ret)
--		goto err;
-+		/* wait */
-+		ret = tc_wait_link_training(tc, &error);
-+		if (ret)
-+			goto err;
- 
--	if (error) {
--		dev_err(tc->dev, "Link training phase 2 failed: %s\n",
--			training_pattern2_errors[error]);
-+		if (error) {
-+			dev_dbg(tc->dev, "Link training phase 2 failed: %s\n",
-+				training_pattern2_errors[error]);
-+		}else{
-+			break;
-+		}
-+	}
-+	if (retry == 10) {
-+		dev_err(tc->dev, "Link training failed \n");
- 		ret = -ENODEV;
- 		goto err;
- 	}
-diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c
-index c0b26135dbd5..fc2eadda02f8 100644
---- a/drivers/gpu/drm/drm_probe_helper.c
-+++ b/drivers/gpu/drm/drm_probe_helper.c
-@@ -203,7 +203,7 @@ enum drm_mode_status drm_connector_mode_valid(struct drm_connector *connector,
- 	return connector_funcs->mode_valid(connector, mode);
- }
- 
--#define DRM_OUTPUT_POLL_PERIOD (10*HZ)
-+#define DRM_OUTPUT_POLL_PERIOD (3*HZ)
- /**
-  * drm_kms_helper_poll_enable - re-enable output polling.
-  * @dev: drm_device
--- 
-2.31.1
-

board/PSG/iot2050/files/0013-fix-fix-the-hardware-flow-function-of-cp2102n24.patch

@@ -1,53 +0,0 @@
-From 262683aad85419c9b13f1ea59f4c26b36d26d393 Mon Sep 17 00:00:00 2001
-From: Gao Nian <nian.gao@siemens.com>
-Date: Wed, 21 Aug 2019 16:22:30 +0800
-Subject: [PATCH 13/26] fix:fix the hardware flow function of cp2102n24
-
-Signed-off-by: Gao Nian <nian.gao@siemens.com>
----
- drivers/usb/serial/cp210x.c | 14 +++++++++++++-
- 1 file changed, 13 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
-index 7815062ed980..5d50eb092975 100644
---- a/drivers/usb/serial/cp210x.c
-+++ b/drivers/usb/serial/cp210x.c
-@@ -271,6 +271,8 @@ static struct usb_serial_driver cp210x_device = {
- 	.break_ctl		= cp210x_break_ctl,
- 	.set_termios		= cp210x_set_termios,
- 	.tx_empty		= cp210x_tx_empty,
-+	.throttle		= usb_serial_generic_throttle,
-+	.unthrottle		= usb_serial_generic_unthrottle,
- 	.tiocmget		= cp210x_tiocmget,
- 	.tiocmset		= cp210x_tiocmset,
- 	.attach			= cp210x_attach,
-@@ -953,6 +955,7 @@ static void cp210x_get_termios_port(struct usb_serial_port *port,
- 	u32 baud;
- 	u16 bits;
- 	u32 ctl_hs;
-+	u32 flow_repl;
- 
- 	cp210x_read_u32_reg(port, CP210X_GET_BAUDRATE, &baud);
- 
-@@ -1051,8 +1054,17 @@ static void cp210x_get_termios_port(struct usb_serial_port *port,
- 	cp210x_read_reg_block(port, CP210X_GET_FLOW, &flow_ctl,
- 			sizeof(flow_ctl));
- 	ctl_hs = le32_to_cpu(flow_ctl.ulControlHandshake);
-+	flow_repl = le32_to_cpu(flow_ctl.ulFlowReplace);
-+	/* CP210x hardware disables RTS but leaves CTS when in hardware flow control mode and port is closed.
-+	 * This allows data to flow out, but new data will not come into the port.
-+	 * When re-opening the port, if CTS is enabled, then RTS must manually be re-enabled. */
- 	if (ctl_hs & CP210X_SERIAL_CTS_HANDSHAKE) {
--		dev_dbg(dev, "%s - flow control = CRTSCTS\n", __func__);
-+		flow_repl &= ~CP210X_SERIAL_RTS_MASK;
-+        flow_repl |= CP210X_SERIAL_RTS_SHIFT(CP210X_SERIAL_RTS_FLOW_CTL);
-+		dev_dbg(dev, "%s - flow control = CRTSCTS, write ulControlHandshake=0x%08x, ulFlowReplace=0x%08x\n", __func__, ctl_hs, flow_repl);
-+		flow_ctl.ulControlHandshake = cpu_to_le32(ctl_hs);
-+		flow_ctl.ulFlowReplace = cpu_to_le32(flow_repl);
-+		cp210x_write_reg_block(port, CP210X_SET_FLOW, &flow_ctl, sizeof(flow_ctl));
- 		cflag |= CRTSCTS;
- 	} else {
- 		dev_dbg(dev, "%s - flow control = NONE\n", __func__);
--- 
-2.31.1
-

board/PSG/iot2050/files/0014-feat-add-io-expander-pcal9535-support.patch

@@ -1,363 +0,0 @@
-From 82d215294eecb6bed5e2ab929c3734aa07c5bdbf Mon Sep 17 00:00:00 2001
-From: "le.jin" <le.jin@siemens.com>
-Date: Wed, 9 Oct 2019 17:08:43 +0800
-Subject: [PATCH 14/26] feat:add io expander pcal9535 support
-
-Signed-off-by: le.jin <le.jin@siemens.com>
----
- drivers/gpio/gpio-pca953x.c   | 76 ++++++++++++++++++++++++++++++++++-
- drivers/gpio/gpiolib-sysfs.c  | 67 ++++++++++++++++++++++++++++++
- drivers/gpio/gpiolib.c        | 18 +++++++++
- drivers/gpio/gpiolib.h        |  4 ++
- include/asm-generic/gpio.h    |  5 +++
- include/linux/gpio.h          | 10 +++++
- include/linux/gpio/consumer.h |  9 +++++
- include/linux/gpio/driver.h   |  2 +
- 8 files changed, 190 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
-index 70443de224da..4d4fbc6e8131 100644
---- a/drivers/gpio/gpio-pca953x.c
-+++ b/drivers/gpio/gpio-pca953x.c
-@@ -14,6 +14,7 @@
- #include <linux/acpi.h>
- #include <linux/gpio/driver.h>
- #include <linux/gpio/consumer.h>
-+#include <linux/gpio.h>
- #include <linux/i2c.h>
- #include <linux/init.h>
- #include <linux/interrupt.h>
-@@ -137,6 +138,8 @@ struct pca953x_chip {
- 	unsigned gpio_start;
- 	u8 reg_output[MAX_BANK];
- 	u8 reg_direction[MAX_BANK];
-+	u8 reg_pull_en[MAX_BANK];
-+	u8 reg_pull_sel[MAX_BANK];
- 	struct mutex i2c_lock;
- 
- #ifdef CONFIG_GPIO_PCA953X_IRQ
-@@ -287,6 +290,60 @@ static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
- 	return 0;
- }
- 
-+static int pca953x_gpio_set_drive(struct gpio_chip *gc,
-+		unsigned off, unsigned mode)
-+{
-+	struct pca953x_chip *chip;
-+	u8 pull_en_reg_val, pull_sel_reg_val;
-+	int ret = 0;
-+
-+	chip = gpiochip_get_data(gc);
-+
-+	if (PCA_CHIP_TYPE(chip->driver_data) != PCA953X_TYPE)
-+		return -EINVAL;
-+
-+	mutex_lock(&chip->i2c_lock);
-+
-+	switch (mode) {
-+	case GPIOF_DRIVE_PULLUP:
-+		pull_en_reg_val = chip->reg_pull_en[off / BANK_SZ]
-+			| (1u << (off % BANK_SZ));
-+		pull_sel_reg_val = chip->reg_pull_sel[off / BANK_SZ]
-+			| (1u << (off % BANK_SZ));
-+		break;
-+	case GPIOF_DRIVE_PULLDOWN:
-+		pull_en_reg_val = chip->reg_pull_en[off / BANK_SZ]
-+			| (1u << (off % BANK_SZ));
-+		pull_sel_reg_val = chip->reg_pull_sel[off / BANK_SZ]
-+			& ~(1u << (off % BANK_SZ));
-+		break;
-+	case GPIOF_DRIVE_STRONG:
-+	case GPIOF_DRIVE_HIZ:
-+		pull_en_reg_val = chip->reg_pull_en[off / BANK_SZ]
-+			& ~(1u << (off % BANK_SZ));
-+		pull_sel_reg_val = chip->reg_pull_sel[off / BANK_SZ];
-+		break;
-+	default:
-+		ret = -EINVAL;
-+		goto exit;
-+	}
-+
-+	ret = pca953x_write_single(chip, PCAL953X_PULL_EN,
-+				pull_en_reg_val, off);
-+	if (ret)
-+		goto exit;
-+	chip->reg_pull_en[off / BANK_SZ] = pull_en_reg_val;
-+
-+	ret = pca953x_write_single(chip, PCAL953X_PULL_SEL,
-+				pull_sel_reg_val, off);
-+	if (ret)
-+		goto exit;
-+	chip->reg_pull_sel[off / BANK_SZ] = pull_sel_reg_val;
-+exit:
-+	mutex_unlock(&chip->i2c_lock);
-+	return ret;
-+}
-+
- static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
- {
- 	struct pca953x_chip *chip = gpiochip_get_data(gc);
-@@ -453,6 +510,9 @@ static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
- 	gc->parent = &chip->client->dev;
- 	gc->owner = THIS_MODULE;
- 	gc->names = chip->names;
-+
-+	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
-+		gc->set_drive = pca953x_gpio_set_drive;
- }
- 
- #ifdef CONFIG_GPIO_PCA953X_IRQ
-@@ -723,8 +783,9 @@ static int pca953x_irq_setup(struct pca953x_chip *chip,
- 
- static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
- {
--	int ret;
-+	int i, ret;
- 	u8 val[MAX_BANK];
-+	u32 pull_en_reg_val, pull_sel_reg_val;
- 
- 	chip->regs = &pca953x_regs;
- 
-@@ -737,6 +798,18 @@ static int device_pca953x_init(struct pca953x_chip *chip, u32 invert)
- 	if (ret)
- 		goto out;
- 
-+	for (i = 0; i < NBANK(chip); i++) {
-+		ret = pca953x_read_single(chip, PCAL953X_PULL_EN, &pull_en_reg_val, i*BANK_SZ);
-+		chip->reg_pull_en[i] = (u8)pull_en_reg_val;
-+		if (ret)
-+			goto out;
-+
-+		ret = pca953x_read_single(chip, PCAL953X_PULL_SEL, &pull_sel_reg_val, i*BANK_SZ);
-+		chip->reg_pull_sel[i] = (u8)pull_sel_reg_val;
-+		if (ret)
-+			goto out;
-+	}
-+
- 	/* set platform specific polarity inversion */
- 	if (invert)
- 		memset(val, 0xFF, NBANK(chip));
-@@ -957,6 +1030,7 @@ static const struct of_device_id pca953x_dt_ids[] = {
- 	{ .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
- 	{ .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), },
- 	{ .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
-+	{ .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_INT | PCA_PCAL), },
- 	{ .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },
- 	{ .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), },
- 	{ .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), },
-diff --git a/drivers/gpio/gpiolib-sysfs.c b/drivers/gpio/gpiolib-sysfs.c
-index 3dbaf489a8a5..ace48f06bc35 100644
---- a/drivers/gpio/gpiolib-sysfs.c
-+++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -362,6 +362,72 @@ static ssize_t active_low_store(struct device *dev,
- }
- static DEVICE_ATTR_RW(active_low);
- 
-+static ssize_t drive_show(struct device *dev,
-+		struct device_attribute *attr, char *buf)
-+{
-+	struct gpiod_data *data = dev_get_drvdata(dev);
-+	struct gpio_desc *desc = data->desc;
-+	ssize_t			status;
-+
-+	mutex_lock(&data->mutex);
-+
-+	if (test_bit(FLAG_PULLUP, &desc->flags))
-+		status = sprintf(buf, "pullup\n");
-+	else if (test_bit(FLAG_PULLDOWN, &desc->flags))
-+		status = sprintf(buf, "pulldown\n");
-+	else if (test_bit(FLAG_STRONG, &desc->flags))
-+		status = sprintf(buf, "strong\n");
-+	else if (test_bit(FLAG_HIZ, &desc->flags))
-+		status = sprintf(buf, "hiz\n");
-+	else
-+		status = -EINVAL;
-+
-+	mutex_unlock(&data->mutex);
-+	return status;
-+}
-+
-+static ssize_t drive_store(struct device *dev,
-+		struct device_attribute *attr, const char *buf, size_t size)
-+{
-+	struct gpiod_data *data = dev_get_drvdata(dev);
-+	struct gpio_desc *desc = data->desc;
-+	ssize_t			status;
-+
-+	mutex_lock(&data->mutex);
-+
-+	clear_bit(FLAG_PULLUP, &desc->flags);
-+	clear_bit(FLAG_PULLDOWN, &desc->flags);
-+	clear_bit(FLAG_STRONG, &desc->flags);
-+	clear_bit(FLAG_HIZ, &desc->flags);
-+	if (sysfs_streq(buf, "pullup")) {
-+		status = gpiod_set_drive(desc, GPIOF_DRIVE_PULLUP);
-+		if (!status) {
-+			set_bit(FLAG_PULLUP, &desc->flags);
-+		}
-+	} else if (sysfs_streq(buf, "pulldown")) {
-+		status = gpiod_set_drive(desc, GPIOF_DRIVE_PULLDOWN);
-+		if (!status) {
-+			set_bit(FLAG_PULLDOWN, &desc->flags);
-+		}
-+	} else if (sysfs_streq(buf, "strong")) {
-+		status = gpiod_set_drive(desc, GPIOF_DRIVE_STRONG);
-+		if (!status) {
-+			set_bit(FLAG_STRONG, &desc->flags);
-+		}
-+	} else if (sysfs_streq(buf, "hiz")) {
-+		status = gpiod_set_drive(desc, GPIOF_DRIVE_HIZ);
-+		if (!status) {
-+			set_bit(FLAG_HIZ, &desc->flags);
-+		}
-+	} else {
-+		status = -EINVAL;
-+	}
-+
-+	mutex_unlock(&data->mutex);
-+	return status ? : size;
-+}
-+static DEVICE_ATTR_RW(drive);
-+
- static umode_t gpio_is_visible(struct kobject *kobj, struct attribute *attr,
- 			       int n)
- {
-@@ -389,6 +455,7 @@ static struct attribute *gpio_attrs[] = {
- 	&dev_attr_edge.attr,
- 	&dev_attr_value.attr,
- 	&dev_attr_active_low.attr,
-+	&dev_attr_drive.attr,
- 	NULL,
- };
- 
-diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
-index a24f13df42f4..9846dee63be5 100644
---- a/drivers/gpio/gpiolib.c
-+++ b/drivers/gpio/gpiolib.c
-@@ -2798,6 +2798,24 @@ int gpiod_is_active_low(const struct gpio_desc *desc)
- }
- EXPORT_SYMBOL_GPL(gpiod_is_active_low);
- 
-+int gpiod_set_drive(struct gpio_desc *desc, unsigned mode)
-+{
-+	struct gpio_chip	*chip;
-+
-+	VALIDATE_DESC(desc);
-+	chip = desc->gdev->chip;
-+	if (!chip || !chip->set || !chip->set_drive)
-+		goto fail;
-+
-+	might_sleep_if(chip->can_sleep);
-+
-+	return chip->set_drive(chip, gpio_chip_hwgpio(desc), mode);
-+
-+fail:
-+	return -EINVAL;
-+}
-+EXPORT_SYMBOL_GPL(gpiod_set_drive);
-+
- /* I/O calls are only valid after configuration completed; the relevant
-  * "is this a valid GPIO" error checks should already have been done.
-  *
-diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h
-index a7e49fef73d4..6c3abc5ecbcf 100644
---- a/drivers/gpio/gpiolib.h
-+++ b/drivers/gpio/gpiolib.h
-@@ -216,6 +216,10 @@ struct gpio_desc {
- #define FLAG_USED_AS_IRQ 9	/* GPIO is connected to an IRQ */
- #define FLAG_IS_HOGGED	11	/* GPIO is hogged */
- #define FLAG_TRANSITORY 12	/* GPIO may lose value in sleep or reset */
-+#define FLAG_PULLUP	13	/* Gpio drive is resistive pullup */
-+#define FLAG_PULLDOWN	14	/* Gpio drive is resistive pulldown */
-+#define FLAG_STRONG	15	/* Gpio drive is strong (fast output) */
-+#define FLAG_HIZ	16	/* Gpio drive is Hi-Z (input) */
- 
- 	/* Connection label */
- 	const char		*label;
-diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
-index 19eadac415c4..4cbba8308161 100644
---- a/include/asm-generic/gpio.h
-+++ b/include/asm-generic/gpio.h
-@@ -81,6 +81,11 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
- 	return gpiod_set_debounce(gpio_to_desc(gpio), debounce);
- }
- 
-+static inline int gpio_set_drive(unsigned gpio, unsigned mode)
-+{
-+	return gpiod_set_drive(gpio_to_desc(gpio), mode);
-+}
-+
- static inline int gpio_get_value_cansleep(unsigned gpio)
- {
- 	return gpiod_get_raw_value_cansleep(gpio_to_desc(gpio));
-diff --git a/include/linux/gpio.h b/include/linux/gpio.h
-index b3115d1a7d49..0dcea09debd5 100644
---- a/include/linux/gpio.h
-+++ b/include/linux/gpio.h
-@@ -41,6 +41,11 @@
- #define GPIOF_EXPORT_DIR_FIXED	(GPIOF_EXPORT)
- #define GPIOF_EXPORT_DIR_CHANGEABLE (GPIOF_EXPORT | GPIOF_EXPORT_CHANGEABLE)
- 
-+#define GPIOF_DRIVE_PULLUP	(1 << 7)
-+#define GPIOF_DRIVE_PULLDOWN	(1 << 8)
-+#define GPIOF_DRIVE_STRONG	(1 << 9)
-+#define GPIOF_DRIVE_HIZ		(1 << 10)
-+
- /**
-  * struct gpio - a structure describing a GPIO with configuration
-  * @gpio:	the GPIO number
-@@ -159,6 +164,11 @@ static inline int gpio_set_debounce(unsigned gpio, unsigned debounce)
- 	return -ENOSYS;
- }
- 
-+static inline int gpio_set_drive(unsigned gpio, unsigned mode)
-+{
-+	return -ENOSYS;
-+}
-+
- static inline int gpio_get_value(unsigned gpio)
- {
- 	/* GPIO can never have been requested or set as {in,out}put */
-diff --git a/include/linux/gpio/consumer.h b/include/linux/gpio/consumer.h
-index 8dfd8300d9c3..30093b6552b5 100644
---- a/include/linux/gpio/consumer.h
-+++ b/include/linux/gpio/consumer.h
-@@ -138,6 +138,8 @@ int gpiod_set_raw_array_value_cansleep(unsigned int array_size,
- int gpiod_set_debounce(struct gpio_desc *desc, unsigned debounce);
- int gpiod_set_transitory(struct gpio_desc *desc, bool transitory);
- 
-+int gpiod_set_drive(struct gpio_desc *desc, unsigned mode);
-+
- int gpiod_is_active_low(const struct gpio_desc *desc);
- int gpiod_cansleep(const struct gpio_desc *desc);
- 
-@@ -445,6 +447,13 @@ static inline int gpiod_set_transitory(struct gpio_desc *desc, bool transitory)
- 	return -ENOSYS;
- }
- 
-+static inline int gpiod_set_drive(unsigned gpio, unsigned mode)
-+{
-+	/* GPIO can never have been requested */
-+	WARN_ON(1);
-+	return -ENOSYS;
-+}
-+
- static inline int gpiod_is_active_low(const struct gpio_desc *desc)
- {
- 	/* GPIO can never have been requested */
-diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
-index a4d5eb37744a..c3af8cf978f6 100644
---- a/include/linux/gpio/driver.h
-+++ b/include/linux/gpio/driver.h
-@@ -258,6 +258,8 @@ struct gpio_chip {
- 	int			(*set_config)(struct gpio_chip *chip,
- 					      unsigned offset,
- 					      unsigned long config);
-+	int			(*set_drive)(struct gpio_chip *chip,
-+					unsigned offset, unsigned mode);
- 	int			(*to_irq)(struct gpio_chip *chip,
- 						unsigned offset);
- 
--- 
-2.31.1
-

board/PSG/iot2050/files/0016-fix-clear-the-cycle-buffer-of-serial.patch

@@ -1,29 +0,0 @@
-From 9e55cdfbcc1dc9bf32e69b3e896d23d0795179c7 Mon Sep 17 00:00:00 2001
-From: Gao Nian <nian.gao@siemens.com>
-Date: Tue, 26 Nov 2019 09:05:56 +0800
-Subject: [PATCH 16/26] fix:clear the cycle buffer of serial
-
-1.the last residual data will be sent next time
-
-Signed-off-by: Gao Nian <nian.gao@siemens.com>
----
- drivers/tty/serial/8250/8250_omap.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
-index 979e4c861a6b..47d90ed7e96e 100644
---- a/drivers/tty/serial/8250/8250_omap.c
-+++ b/drivers/tty/serial/8250/8250_omap.c
-@@ -706,6 +706,9 @@ static void omap_8250_shutdown(struct uart_port *port)
- 		serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
- 	serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
- 
-+	/* Clear the circ buffuer to clean the residual data */
-+	uart_circ_clear(&port->state->xmit);
-+
- 	pm_runtime_mark_last_busy(port->dev);
- 	pm_runtime_put_autosuspend(port->dev);
- 	free_irq(port->irq, port);
--- 
-2.31.1
-

board/PSG/iot2050/files/0018-fix-can-not-auto-negotiate-to-100M-with-4-wire.patch

@@ -1,102 +0,0 @@
-From 1c7b0a837a2a493e6af9427af52f22404c0be720 Mon Sep 17 00:00:00 2001
-From: Gao Nian <nian.gao@siemens.com>
-Date: Tue, 4 Feb 2020 22:03:52 +0800
-Subject: [PATCH 18/26] fix:can not auto negotiate to 100M with 4-wire
-
-Signed-off-by: Gao Nian <nian.gao@siemens.com>
----
- drivers/net/phy/dp83867.c | 48 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
-diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
-index a35ccaf6bb1b..2d1d3a0d151d 100644
---- a/drivers/net/phy/dp83867.c
-+++ b/drivers/net/phy/dp83867.c
-@@ -27,8 +27,10 @@
- #define DP83867_DEVADDR		0x1f
- 
- #define MII_DP83867_PHYCTRL	0x10
-+#define MII_DP83867_PHYSTS	0x11
- #define MII_DP83867_MICR	0x12
- #define MII_DP83867_ISR		0x13
-+#define DP83867_CFG2		0x14
- #define DP83867_CTRL		0x1f
- #define DP83867_CFG3		0x1e
- 
-@@ -107,6 +109,15 @@
- #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK	(0x1f << 8)
- #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT	8
- 
-+/* PHY STS bits */
-+#define DP83867_PHYSTS_1000			BIT(15)
-+#define DP83867_PHYSTS_100			BIT(14)
-+#define DP83867_PHYSTS_DUPLEX			BIT(13)
-+#define DP83867_PHYSTS_LINK			BIT(10)
-+
-+/* CFG2 bits */
-+#define DP83867_SPEED_OPTOMIZED_EN		(BIT(8) | BIT(9))
-+
- /* CFG3 bits */
- #define DP83867_CFG3_INT_OE			BIT(7)
- #define DP83867_CFG3_ROBUST_AUTO_MDIX		BIT(9)
-@@ -167,6 +178,34 @@ static int dp83867_config_intr(struct phy_device *phydev)
- 	return phy_write(phydev, MII_DP83867_MICR, micr_status);
- }
- 
-+static int dp83867_read_status(struct phy_device *phydev)
-+{
-+	int status = phy_read(phydev, MII_DP83867_PHYSTS);
-+
-+	if (status & DP83867_PHYSTS_DUPLEX)
-+		phydev->duplex = DUPLEX_FULL;
-+	else
-+		phydev->duplex = DUPLEX_HALF;
-+
-+	if (status & DP83867_PHYSTS_1000)
-+		phydev->speed = SPEED_1000;
-+	else if (status & DP83867_PHYSTS_100)
-+		phydev->speed = SPEED_100;
-+	else
-+		phydev->speed = SPEED_10;
-+
-+	if (status & DP83867_PHYSTS_LINK)
-+		phydev->link = 1;
-+	else
-+		phydev->link = 0;
-+
-+	phydev->pause = 0;
-+	phydev->asym_pause = 0;
-+	phydev->lp_advertising = 0;
-+
-+	return 0;
-+}
-+
- static int dp83867_config_port_mirroring(struct phy_device *phydev)
- {
- 	struct dp83867_private *dp83867 =
-@@ -313,6 +352,13 @@ static int dp83867_config_init(struct phy_device *phydev)
- 	int ret, val, bs;
- 	u16 delay;
- 
-+	/* Force the speed opotimization for the PHY even if it strapped */
-+	val = phy_read(phydev, DP83867_CFG2);
-+	val |= DP83867_SPEED_OPTOMIZED_EN;
-+	ret = phy_write(phydev, DP83867_CFG2, val);
-+	if (ret)
-+		return ret;
-+
- 	ret = dp83867_verify_rgmii_cfg(phydev);
- 	if (ret)
- 		return ret;
-@@ -494,6 +540,8 @@ static struct phy_driver dp83867_driver[] = {
- 		.config_init	= dp83867_config_init,
- 		.soft_reset	= dp83867_phy_reset,
- 
-+		.read_status	= dp83867_read_status,
-+
- 		/* IRQ related */
- 		.ack_interrupt	= dp83867_ack_interrupt,
- 		.config_intr	= dp83867_config_intr,
--- 
-2.31.1
-

board/PSG/iot2050/files/0019-feat-change-mmc-order-using-alias-in-dts.patch

@@ -1,62 +0,0 @@
-From ad0018438d0e7ccd4d9a1dd8758162c53dbcfd79 Mon Sep 17 00:00:00 2001
-From: Su Baocheng <baocheng.su@siemens.com>
-Date: Tue, 22 Dec 2020 15:08:17 +0800
-Subject: [PATCH 19/26] feat:change mmc order using alias in dts
-
-1. modify kernel to support mmc alias in dts
-2. change SD to mmc0 and EMMC to mmc1 via alias in dts
-
-Signed-off-by: Gao Nian <nian.gao@siemens.com>
----
- drivers/mmc/core/host.c | 23 ++++++++++++++++++-----
- 1 file changed, 18 insertions(+), 5 deletions(-)
-
-diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
-index f57f5de54206..5db720c6591b 100644
---- a/drivers/mmc/core/host.c
-+++ b/drivers/mmc/core/host.c
-@@ -357,8 +357,8 @@ EXPORT_SYMBOL(mmc_of_parse);
-  */
- struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
- {
--	int err;
- 	struct mmc_host *host;
-+	int of_id = -1, id = -1;
- 
- 	host = kzalloc(sizeof(struct mmc_host) + extra, GFP_KERNEL);
- 	if (!host)
-@@ -367,14 +367,27 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev)
- 	/* scanning will be enabled when we're ready */
- 	host->rescan_disable = 1;
- 
--	err = ida_simple_get(&mmc_host_ida, 0, 0, GFP_KERNEL);
--	if (err < 0) {
-+	if (dev->of_node) {
-+		of_id = of_alias_get_id(dev->of_node, "mmc");
-+	}
-+
-+	if (of_id >= 0) {
-+		id = ida_simple_get(&mmc_host_ida, of_id, of_id + 1, GFP_NOWAIT);
-+		if (id < 0)
-+			dev_warn(dev, "aliases ID %d not available\n", of_id);
-+	}
-+
-+	if (id < 0)
-+		id = ida_simple_get(&mmc_host_ida, 0, 0, GFP_NOWAIT);
-+
-+	if (id >= 0)
-+		host->index = id;
-+
-+	if (id < 0) {
- 		kfree(host);
- 		return NULL;
- 	}
- 
--	host->index = err;
--
- 	dev_set_name(&host->class_dev, "mmc%d", host->index);
- 
- 	host->parent = dev;
--- 
-2.31.1
-

board/PSG/iot2050/files/0020-fix-PLL4_DCO-freq-over-range-cause-DP-not-display.patch

@@ -1,250 +0,0 @@
-From 1c9d8953f936f6e1beee71af59aa5e2533be0ef1 Mon Sep 17 00:00:00 2001
-From: chao zeng <chao.zeng@siemens.com>
-Date: Fri, 11 Dec 2020 17:20:12 +0800
-Subject: [PATCH 20/26] fix:PLL4_DCO freq over range cause DP not display
-
-  1.some DP may be can not display.
-  2.reason: TI sysfw can not correct set PLL4 some frequency
-            division parameter(M,N,M2),It will cause DCO over range,
-            calculate DCO frequency not between HS1 and HS2 mode,
-            So,CLKOUT is bypass mode,only out 25Mhz,Then DSS_PLL_CLKOUT
-            and DPI_1_IN_CLK is always 25MHz,and It don't match the
-            frequency of the monitor,so can not display.
-
-            so,through dynamic acquisition of monitor frequency(Rate),
-            calculation (M,N,M2) value and set correlation register.
-
-Signed-off-by: Sheng Long Wang <shenglong.wang.ext@siemens.com>
----
- drivers/gpu/drm/tidss/tidss_dispc7.c | 196 +++++++++++++++++++++++++++
- 1 file changed, 196 insertions(+)
-
-diff --git a/drivers/gpu/drm/tidss/tidss_dispc7.c b/drivers/gpu/drm/tidss/tidss_dispc7.c
-index 32f7535a0f83..b43cd213b6d9 100644
---- a/drivers/gpu/drm/tidss/tidss_dispc7.c
-+++ b/drivers/gpu/drm/tidss/tidss_dispc7.c
-@@ -33,6 +33,19 @@
- #include "tidss_scale_coefs.h"
- #include "tidss_dispc7.h"
- 
-+#define DSS_PLL_BASE_ADDR	0x00684000
-+#define PLL_KICK0_OFFSET	0x0010
-+#define PLL_KICK1_OFFSET	0x0014
-+#define PLL_FREQ_CTRL0_OFFSET	0x0020
-+#define PLL_FREQ_CTRL1_OFFSET	0x0024
-+#define PLL_CLKDIV_OFFSET	0x0028
-+#define PLL_PROG_OFFSET		0x002C
-+#define PLL_CTRL_OFFSET		0x0030
-+#define PLL_STAT_OFFSET		0x0034
-+#define KICK0_UNLOCK		0x68EF3490
-+#define KICK1_UNLOCK		0xD172BC5A
-+#define KICK_LOCK		0x00000000
-+
- static const char *dispc7_plane_name(struct dispc_device *dispc, u32 hw_plane);
- 
- static const struct dispc7_features dispc7_am6_feats = {
-@@ -1122,11 +1135,139 @@ static unsigned int dispc7_pclk_diff(unsigned long rate,
- 	return (unsigned int)(abs(((rr - r) * 100) / r));
- }
- 
-+static void dss_pll4_reg_write(u32 reg, u32 val)
-+{
-+	void __iomem *regval;
-+
-+	regval = ioremap(DSS_PLL_BASE_ADDR + reg ,SZ_4);
-+	writel(val, regval);
-+	mdelay(2);
-+	iounmap(regval);
-+}
-+
-+static u32 dss_pll4_reg_read(u32 reg)
-+{
-+	void __iomem *regval;
-+	u32 data;
-+
-+	regval = ioremap(DSS_PLL_BASE_ADDR + reg,SZ_4);
-+	data = readl(regval);
-+	iounmap(regval);
-+
-+	return data;
-+}
-+
-+static int get_dp_clock_parameter(int Rate, u16 *M_INT, u8 *N_DIV, u8 *M2, u8 *choose_flag)
-+{
-+	u16 m2_div[127] = {0};
-+	u16 result[127][3] = {0};
-+	u16 hs2_dco_freq   = 0;
-+	u16 hs1_dco_freq   = 0;
-+	u16 start,ck,N,M;
-+	u16 first = 0, second = 0, mid = 0;
-+
-+	u8  hs2_data_exist = 0;
-+	u8  hs1_data_exist = 0;
-+	u8  count = 0, ret = 0, i = 0;
-+
-+	if (Rate < 6 || Rate > 2500) {
-+		return 0;
-+	}
-+
-+	for (start = 750 / Rate + (750%Rate!=0); start <= 2500 / Rate; ++start) {
-+		if (start >= 1 && start <= 127) {
-+			m2_div[count] = start;
-+			count++;
-+		}
-+	}
-+
-+	for (i = 0; i < count; ++i) {
-+		ck = Rate * m2_div[i];
-+		for ( N = 0; N <= 255; ++N) {
-+			M = (N + 1) * ck / 25;
-+			if ((M * 25 == (N + 1) * ck) && (M >= 2) && (M <= 4095)) {
-+			printk(KERN_DEBUG "M2=%d, N=%d, M=%d\n", m2_div[i], N, M);
-+			result[i][0] = m2_div[i];
-+			result[i][1] = M;
-+			result[i][2] = N;
-+			ret = 1;
-+			}
-+		}
-+	}
-+
-+	if (!ret) {
-+		return 0;
-+	}
-+
-+	for (i = 0; i < count; ++i) {
-+		if (Rate * m2_div[i] <= 1500) first++;
-+		if (Rate * m2_div[i] >= 1250)
-+			second++;
-+		else
-+			mid++;
-+	}
-+
-+	if (first == 0) {
-+		hs2_data_exist = 1;
-+	}
-+
-+	if (second == 0) {
-+		hs1_data_exist = 1;
-+	}
-+
-+	if((hs1_data_exist == 0) && (hs2_data_exist == 0)) {
-+		hs2_dco_freq = 25 * result[first / 2][1] / (result[first / 2][2] + 1);
-+		hs1_dco_freq = 25 * result[second / 2 + mid][1]  / ( result[second / 2 + mid][2] +1);
-+
-+		if ((abs(hs2_dco_freq - 1125) > abs(hs1_dco_freq - 1875))) {
-+			printk(KERN_DEBUG "(hs1 mode) [1250-2500] : M2=%d, M=%d, N=%d\n",
-+				result[second / 2 + mid][0], result[second / 2 + mid][1], result[second / 2 + mid][2]);
-+			*M_INT = (u16)(result[second / 2 + mid][1]);
-+			*N_DIV = (u8)(result[second  / 2 + mid][2]);
-+			*M2    = (u8)(result[second  / 2 + mid][0]);
-+			*choose_flag = 2;
-+		} else {
-+			printk(KERN_DEBUG "(hs2 mode)[750-1500] : M2=%d, M=%d, N=%d\n",
-+				result[first / 2][0], result[first / 2][1], result[first / 2][2]);
-+			*M_INT = (u16)(result[first / 2][1]);
-+			*N_DIV = (u8)(result[first  / 2][2]);
-+			*M2    = (u8)(result[first  / 2][0]);
-+			*choose_flag = 1;
-+		}
-+	} else {
-+		if ((hs2_data_exist == 0) && (hs1_data_exist == 1)) {
-+			printk(KERN_DEBUG "(hs2 mode)[750-1500]   : M2=%d, M=%d, N=%d\n",
-+				result[first / 2][0], result[first / 2][1], result[first / 2][2]);
-+			*M_INT = (u16)(result[first / 2][1]);
-+			*N_DIV = (u8)(result[first  / 2][2]);
-+			*M2    = (u8)(result[first  / 2][0]);
-+			*choose_flag = 1;
-+		} else if ((hs2_data_exist == 1) && (hs1_data_exist == 0)) {
-+				printk(KERN_DEBUG "(hs1 mode)[1250--2500] : M2=%d, M=%d, N=%d\n",
-+					result[second / 2 + mid][0], result[second / 2 + mid][1], result[second / 2 + mid][2]);
-+				*M_INT = (u16)(result[second / 2 + mid][1]);
-+				*N_DIV = (u8)(result[second  / 2 + mid][2]);
-+				*M2    = (u8)(result[second  / 2 + mid][0]);
-+				*choose_flag = 2;
-+		} else {
-+			return 0;
-+		}
-+	}
-+
-+	return 1;
-+}
-+
-+
- static int dispc7_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
- 				  unsigned long rate)
- {
- 	int r;
- 	unsigned long new_rate;
-+	u32 data;
-+	u16 M_INT;
-+	u8  N_DIV;
-+	u8  M2;
-+	u8  choose_flag = 0;
- 
- 	r = clk_set_rate(dispc->vp_clk[hw_videoport], rate);
- 	if (r) {
-@@ -1145,6 +1286,61 @@ static int dispc7_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
- 	dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n",
- 		hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate);
- 
-+	/**dynamic Get (M,N,M2) value**/
-+	r = get_dp_clock_parameter(rate/1000000, &M_INT, &N_DIV, &M2, &choose_flag);
-+	if(!r){
-+		dev_err(dispc->dev,"get DP PLL parameter erro \n");
-+		return 0;
-+	}
-+	mdelay(2);
-+
-+	/**Unlock PLL registers**/
-+	dss_pll4_reg_write(PLL_KICK0_OFFSET,KICK0_UNLOCK);
-+	dss_pll4_reg_write(PLL_KICK1_OFFSET,KICK1_UNLOCK);
-+
-+	/**Switch PLL outputs to bypass freq**/
-+	dss_pll4_reg_write(PLL_CTRL_OFFSET,0x2100099);
-+
-+	/**Prepare PLL for programming**/
-+	dss_pll4_reg_write(PLL_PROG_OFFSET,0);
-+
-+	/** DSS Clock Set **/
-+	data = dss_pll4_reg_read(PLL_FREQ_CTRL0_OFFSET);
-+	data &= 0xFFF00000;  //clear bit [0:19]
-+	data |= (u32)N_DIV;
-+	data |= (u32)(M_INT << 8);
-+	dss_pll4_reg_write(PLL_FREQ_CTRL0_OFFSET,data);  //set M,N
-+	if(choose_flag == 1)
-+		dss_pll4_reg_write(PLL_FREQ_CTRL1_OFFSET,0x02000000);  //set M.f HS2
-+	else if (choose_flag == 2)
-+		dss_pll4_reg_write(PLL_FREQ_CTRL1_OFFSET,0x04000000);  //set M.f HS1
-+
-+
-+	/**Set  M2 **/
-+	data = dss_pll4_reg_read(PLL_CLKDIV_OFFSET);
-+	data &= ~((0x7F << 8));  //clear bit [8:14]
-+	data |= (u32)(M2 << 8);
-+	dss_pll4_reg_write(PLL_CLKDIV_OFFSET,data);
-+
-+	/**Trigger PLL update to new values**/
-+	dss_pll4_reg_write(PLL_PROG_OFFSET,0x2);
-+
-+	/**Trigger PLL update to new values**/
-+	dss_pll4_reg_write(PLL_PROG_OFFSET,0x102);
-+
-+	/** Trigger PLL lock to new values**/
-+	dss_pll4_reg_write(PLL_PROG_OFFSET,0x103);
-+
-+	/** Send PLL to idle**/
-+	dss_pll4_reg_write(PLL_PROG_OFFSET,0x1);
-+
-+	/** Switch PLL outputs to locked freq**/
-+	dss_pll4_reg_write(PLL_CTRL_OFFSET,0x2100019);
-+
-+	/**Lock PLL registers **/
-+	dss_pll4_reg_write(PLL_KICK0_OFFSET,KICK_LOCK);
-+	dss_pll4_reg_write(PLL_KICK1_OFFSET,KICK_LOCK);
-+
- 	return 0;
- }
- 
--- 
-2.31.1
-

board/PSG/iot2050/files/0021-serial-8250-8250_omap-Fix-possible-interrupt-storm-o.patch

@@ -1,89 +0,0 @@
-From a362a6b9454b201b1e75b68da50366905eb5b613 Mon Sep 17 00:00:00 2001
-From: Vignesh Raghavendra <vigneshr@ti.com>
-Date: Tue, 22 Jun 2021 20:27:04 +0530
-Subject: [PATCH 21/26] serial: 8250: 8250_omap: Fix possible interrupt storm
- on K3 SoCs
-
-[upstream commit b67e830d38fa9335d927fe67e812e3ed81b4689c]
-
-On K3 family of SoCs (which includes AM654 SoC), it is observed that RX
-TIMEOUT is signalled after RX FIFO has been drained, in which case a
-dummy read of RX FIFO is required to clear RX TIMEOUT condition.
-Otherwise, this would lead to an interrupt storm.
-
-Fix this by introducing UART_RX_TIMEOUT_QUIRK flag and doing a dummy
-read in IRQ handler when RX TIMEOUT is reported with no data in RX FIFO.
-
-Fixes: be70874498f3 ("serial: 8250_omap: Add support for AM654 UART controller")
-Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
-Tested-by: Jan Kiszka <jan.kiszka@siemens.com>
-Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
-Link: https://lore.kernel.org/r/20210622145704.11168-1-vigneshr@ti.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-[Jan: backported]
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
----
- drivers/tty/serial/8250/8250_omap.c | 19 ++++++++++++++++++-
- 1 file changed, 18 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/tty/serial/8250/8250_omap.c b/drivers/tty/serial/8250/8250_omap.c
-index 47d90ed7e96e..fc53c0ae3d87 100644
---- a/drivers/tty/serial/8250/8250_omap.c
-+++ b/drivers/tty/serial/8250/8250_omap.c
-@@ -41,6 +41,7 @@
-  */
- #define UART_ERRATA_CLOCK_DISABLE	(1 << 3)
- #define	UART_HAS_EFR2			BIT(4)
-+#define UART_RX_TIMEOUT_QUIRK		BIT(6)
- 
- #define OMAP_UART_FCR_RX_TRIG		6
- #define OMAP_UART_FCR_TX_TRIG		4
-@@ -98,6 +99,9 @@
- #define UART_OMAP_EFR2			0x23
- #define UART_OMAP_EFR2_TIMEOUT_BEHAVE	BIT(6)
- 
-+/* RX FIFO occupancy indicator */
-+#define UART_OMAP_RX_LVL		0x64
-+
- struct omap8250_priv {
- 	int line;
- 	u8 habit;
-@@ -593,6 +597,7 @@ static int omap_8250_dma_handle_irq(struct uart_port *port);
- static irqreturn_t omap8250_irq(int irq, void *dev_id)
- {
- 	struct uart_port *port = dev_id;
-+	struct omap8250_priv *priv = port->private_data;
- 	struct uart_8250_port *up = up_to_u8250p(port);
- 	unsigned int iir;
- 	int ret;
-@@ -607,6 +612,18 @@ static irqreturn_t omap8250_irq(int irq, void *dev_id)
- 	serial8250_rpm_get(up);
- 	iir = serial_port_in(port, UART_IIR);
- 	ret = serial8250_handle_irq(port, iir);
-+
-+	/*
-+	 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
-+	 * FIFO has been drained, in which case a dummy read of RX FIFO
-+	 * is required to clear RX TIMEOUT condition.
-+	 */
-+	if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
-+	    (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
-+	    serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
-+		serial_port_in(port, UART_RX);
-+	}
-+
- 	serial8250_rpm_put(up);
- 
- 	return IRQ_RETVAL(ret);
-@@ -1207,7 +1224,7 @@ static struct omap8250_dma_params am33xx_dma = {
- 
- static struct omap8250_platdata am654_platdata = {
- 	.dma_params	= &am654_dma,
--	.habit		= UART_HAS_EFR2,
-+	.habit		= UART_HAS_EFR2 | UART_RX_TIMEOUT_QUIRK,
- };
- 
- static struct omap8250_platdata am33xx_platdata = {
--- 
-2.31.1
-

board/PSG/iot2050/files/0022-watchdog-add-support-for-adjusting-last-known-HW-kee.patch

@@ -1,100 +0,0 @@
-From 98a7ab6a800c9ba933eb2d07758c623ab73a3ffd Mon Sep 17 00:00:00 2001
-From: Tero Kristo <t-kristo@ti.com>
-Date: Fri, 17 Jul 2020 16:29:56 +0300
-Subject: [PATCH 22/26] watchdog: add support for adjusting last known HW
- keepalive time
-
-Certain watchdogs require the watchdog only to be pinged within a
-specific time window, pinging too early or too late cause the watchdog
-to fire. In cases where this sort of watchdog has been started before
-kernel comes up, we must adjust the watchdog keepalive window to match
-the actually running timer, so add a new driver API for this purpose.
-
-Signed-off-by: Tero Kristo <t-kristo@ti.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20200717132958.14304-3-t-kristo@ti.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- .../watchdog/watchdog-kernel-api.txt          | 12 ++++++++
- drivers/watchdog/watchdog_dev.c               | 30 +++++++++++++++++++
- include/linux/watchdog.h                      |  2 ++
- 3 files changed, 44 insertions(+)
-
-diff --git a/Documentation/watchdog/watchdog-kernel-api.txt b/Documentation/watchdog/watchdog-kernel-api.txt
-index 9b93953f69cf..37918242bd63 100644
---- a/Documentation/watchdog/watchdog-kernel-api.txt
-+++ b/Documentation/watchdog/watchdog-kernel-api.txt
-@@ -307,3 +307,15 @@ an action is taken by a preconfigured pretimeout governor preassigned to
- the watchdog device. If watchdog pretimeout governor framework is not
- enabled, watchdog_notify_pretimeout() prints a notification message to
- the kernel log buffer.
-+
-+To set the last known HW keepalive time for a watchdog, the following function
-+should be used::
-+
-+  int watchdog_set_last_hw_keepalive(struct watchdog_device *wdd,
-+                                     unsigned int last_ping_ms)
-+
-+This function must be called immediately after watchdog registration. It
-+sets the last known hardware heartbeat to have happened last_ping_ms before
-+current time. Calling this is only needed if the watchdog is already running
-+when probe is called, and the watchdog can only be pinged after the
-+min_hw_heartbeat_ms time has passed from the last ping.
-diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
-index e47a59a0e7a6..6d8f8e798ca7 100644
---- a/drivers/watchdog/watchdog_dev.c
-+++ b/drivers/watchdog/watchdog_dev.c
-@@ -1121,6 +1121,36 @@ void watchdog_dev_unregister(struct watchdog_device *wdd)
- 	watchdog_cdev_unregister(wdd);
- }
- 
-+/*
-+ *	watchdog_set_last_hw_keepalive: set last HW keepalive time for watchdog
-+ *	@wdd: watchdog device
-+ *	@last_ping_ms: time since last HW heartbeat
-+ *
-+ *	Adjusts the last known HW keepalive time for a watchdog timer.
-+ *	This is needed if the watchdog is already running when the probe
-+ *	function is called, and it can't be pinged immediately. This
-+ *	function must be called immediately after watchdog registration,
-+ *	and min_hw_heartbeat_ms must be set for this to be useful.
-+ */
-+int watchdog_set_last_hw_keepalive(struct watchdog_device *wdd,
-+				   unsigned int last_ping_ms)
-+{
-+	struct watchdog_core_data *wd_data;
-+	ktime_t now;
-+
-+	if (!wdd)
-+		return -EINVAL;
-+
-+	wd_data = wdd->wd_data;
-+
-+	now = ktime_get();
-+
-+	wd_data->last_hw_keepalive = ktime_sub(now, ms_to_ktime(last_ping_ms));
-+
-+	return __watchdog_ping(wdd);
-+}
-+EXPORT_SYMBOL_GPL(watchdog_set_last_hw_keepalive);
-+
- /*
-  *	watchdog_dev_init: init dev part of watchdog core
-  *
-diff --git a/include/linux/watchdog.h b/include/linux/watchdog.h
-index bebcb4f196dc..0ef61627ee55 100644
---- a/include/linux/watchdog.h
-+++ b/include/linux/watchdog.h
-@@ -214,6 +214,8 @@ extern int watchdog_init_timeout(struct watchdog_device *wdd,
- extern int watchdog_register_device(struct watchdog_device *);
- extern void watchdog_unregister_device(struct watchdog_device *);
- 
-+int watchdog_set_last_hw_keepalive(struct watchdog_device *, unsigned int);
-+
- /* devres register variant */
- int devm_watchdog_register_device(struct device *dev, struct watchdog_device *);
- 
--- 
-2.31.1
-

board/PSG/iot2050/files/0023-watchdog-use-__watchdog_ping-in-startup.patch

@@ -1,59 +0,0 @@
-From 1efe9a588b11699518949ff117a30391098946a1 Mon Sep 17 00:00:00 2001
-From: Tero Kristo <t-kristo@ti.com>
-Date: Fri, 17 Jul 2020 16:29:55 +0300
-Subject: [PATCH 23/26] watchdog: use __watchdog_ping in startup
-
-[upstream commit fbbe35dfcf949f4d6cf987648e52a85fc0c2a23a]
-
-Current watchdog startup functionality does not respect the minimum hw
-heartbeat setup and the last watchdog ping timeframe when watchdog is
-already running and userspace process attaches to it. Fix this by using
-the __watchdog_ping from the startup also. For this code path, we can
-also let the __watchdog_ping handle the bookkeeping for the worker and
-last keepalive times.
-
-Signed-off-by: Tero Kristo <t-kristo@ti.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20200717132958.14304-2-t-kristo@ti.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
-[Jan: backported]
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
----
- drivers/watchdog/watchdog_dev.c | 18 ++++++++++--------
- 1 file changed, 10 insertions(+), 8 deletions(-)
-
-diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
-index 6d8f8e798ca7..8965aabb9d59 100644
---- a/drivers/watchdog/watchdog_dev.c
-+++ b/drivers/watchdog/watchdog_dev.c
-@@ -258,16 +258,18 @@ static int watchdog_start(struct watchdog_device *wdd)
- 	set_bit(_WDOG_KEEPALIVE, &wd_data->status);
- 
- 	started_at = ktime_get();
--	if (watchdog_hw_running(wdd) && wdd->ops->ping)
--		err = wdd->ops->ping(wdd);
--	else
-+	if (watchdog_hw_running(wdd) && wdd->ops->ping) {
-+		err = __watchdog_ping(wdd);
-+		if (err == 0)
-+			set_bit(WDOG_ACTIVE, &wdd->status);
-+	} else {
- 		err = wdd->ops->start(wdd);
--	if (err == 0) {
--		set_bit(WDOG_ACTIVE, &wdd->status);
--		wd_data->last_keepalive = started_at;
--		watchdog_update_worker(wdd);
--		if (test_bit(WDOG_RESET_KEEPALIVE, &wdd->status))
-+		if (err == 0) {
-+			set_bit(WDOG_ACTIVE, &wdd->status);
-+			wd_data->last_keepalive = started_at;
- 			wd_data->last_hw_keepalive = started_at;
-+			watchdog_update_worker(wdd);
-+		}
- 	}
- 
- 	return err;
--- 
-2.31.1
-

board/PSG/iot2050/files/0024-watchdog-Respect-handle_boot_enabled-when-setting-la.patch

@@ -1,34 +0,0 @@
-From 96bec6cf59b8744e3382b6ecff5c0502e3fce83d Mon Sep 17 00:00:00 2001
-From: Jan Kiszka <jan.kiszka@siemens.com>
-Date: Fri, 30 Jul 2021 21:19:38 +0200
-Subject: [PATCH 24/26] watchdog: Respect handle_boot_enabled when setting last
- last_hw_keepalive
-
-We must not pet a running watchdog when handle_boot_enabled is off
-because this requests to only start doing that via userspace, not during
-probing.
-
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
----
- drivers/watchdog/watchdog_dev.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/watchdog/watchdog_dev.c b/drivers/watchdog/watchdog_dev.c
-index 8965aabb9d59..d5e949a976dc 100644
---- a/drivers/watchdog/watchdog_dev.c
-+++ b/drivers/watchdog/watchdog_dev.c
-@@ -1149,7 +1149,10 @@ int watchdog_set_last_hw_keepalive(struct watchdog_device *wdd,
- 
- 	wd_data->last_hw_keepalive = ktime_sub(now, ms_to_ktime(last_ping_ms));
- 
--	return __watchdog_ping(wdd);
-+	if (handle_boot_enabled)
-+		return __watchdog_ping(wdd);
-+
-+	return 0;
- }
- EXPORT_SYMBOL_GPL(watchdog_set_last_hw_keepalive);
- 
--- 
-2.31.1
-

board/PSG/iot2050/files/0025-watchdog-rti_wdt-Backport-mainline-driver.patch

@@ -1,354 +0,0 @@
-From 4823856642a29f81c2310a05b4687588c62633fb Mon Sep 17 00:00:00 2001
-From: Jan Kiszka <jan.kiszka@siemens.com>
-Date: Fri, 30 Jul 2021 13:53:20 +0200
-Subject: [PATCH 25/26] watchdog: rti_wdt: Backport mainline driver
-
-Corresponds to 8711071e9700b67045fe5518161d63f7a03e3c9e upstream.
-
-This comes with a lot of improvements, specifically for picking up a
-watchdog already started by the firmware.
-
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
----
- drivers/watchdog/rti_wdt.c | 194 ++++++++++++++++++++++++++++---------
- 1 file changed, 146 insertions(+), 48 deletions(-)
-
-diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c
-index b0933b090f53..e3c90e617c7a 100644
---- a/drivers/watchdog/rti_wdt.c
-+++ b/drivers/watchdog/rti_wdt.c
-@@ -2,26 +2,27 @@
- /*
-  * Watchdog driver for the K3 RTI module
-  *
-- * (c) Copyright 2019 Texas Instruments Inc.
-+ * (c) Copyright 2019-2020 Texas Instruments Inc.
-  * All rights reserved.
-  */
- 
-+#include <linux/clk.h>
-+#include <linux/device.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/kernel.h>
-+#include <linux/mod_devicetable.h>
- #include <linux/module.h>
- #include <linux/moduleparam.h>
--#include <linux/mod_devicetable.h>
--#include <linux/types.h>
--#include <linux/kernel.h>
--#include <linux/watchdog.h>
- #include <linux/platform_device.h>
--#include <linux/io.h>
--#include <linux/device.h>
--#include <linux/clk.h>
--#include <linux/err.h>
- #include <linux/pm_runtime.h>
-+#include <linux/types.h>
-+#include <linux/watchdog.h>
- 
--#define MODULE_NAME "rti-wdt"
- #define DEFAULT_HEARTBEAT 60
--#define MAX_HEARTBEAT     1000
-+
-+/* Max heartbeat is calculated at 32kHz source clock */
-+#define MAX_HEARTBEAT	1000
- 
- /* Timer register set definition */
- #define RTIDWDCTRL	0x90
-@@ -34,7 +35,11 @@
- 
- #define RTIWWDRX_NMI	0xa
- 
--#define RTIWWDSIZE_50P	0x50
-+#define RTIWWDSIZE_50P		0x50
-+#define RTIWWDSIZE_25P		0x500
-+#define RTIWWDSIZE_12P5		0x5000
-+#define RTIWWDSIZE_6P25		0x50000
-+#define RTIWWDSIZE_3P125	0x500000
- 
- #define WDENABLE_KEY	0xa98559da
- 
-@@ -47,42 +52,45 @@
- 
- #define DWDST			BIT(1)
- 
--static int heartbeat;
-+static int heartbeat = DEFAULT_HEARTBEAT;
- 
- /*
-  * struct to hold data for each WDT device
-  * @base - base io address of WD device
-- * @clk - source clock of WDT
-- * @wdd - hold watchdog device as is in WDT core
-+ * @freq - source clock frequency of WDT
-+ * @wdd  - hold watchdog device as is in WDT core
-  */
- struct rti_wdt_device {
- 	void __iomem		*base;
--	struct clk		*clk;
-+	unsigned long		freq;
- 	struct watchdog_device	wdd;
- };
- 
- static int rti_wdt_start(struct watchdog_device *wdd)
- {
- 	u32 timer_margin;
--	unsigned long freq;
- 	struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
- 
--	freq = clk_get_rate(wdt->clk);
--
- 	/* set timeout period */
--	timer_margin = (u64)wdd->timeout * freq;
-+	timer_margin = (u64)wdd->timeout * wdt->freq;
- 	timer_margin >>= WDT_PRELOAD_SHIFT;
- 	if (timer_margin > WDT_PRELOAD_MAX)
- 		timer_margin = WDT_PRELOAD_MAX;
- 	writel_relaxed(timer_margin, wdt->base + RTIDWDPRLD);
- 
--	/* Set min heartbeat to 1.1x window size */
--	wdd->min_hw_heartbeat_ms = 11 * wdd->timeout * 1000 / 20;
-+	/*
-+	 * RTI only supports a windowed mode, where the watchdog can only
-+	 * be petted during the open window; not too early or not too late.
-+	 * The HW configuration options only allow for the open window size
-+	 * to be 50% or less than that; we obviouly want to configure the open
-+	 * window as large as possible so we select the 50% option.
-+	 */
-+	wdd->min_hw_heartbeat_ms = 500 * wdd->timeout;
- 
- 	/* Generate NMI when wdt expires */
- 	writel_relaxed(RTIWWDRX_NMI, wdt->base + RTIWWDRXCTRL);
- 
--	/* Window size 50% */
-+	/* Open window size 50%; this is the largest window size available */
- 	writel_relaxed(RTIWWDSIZE_50P, wdt->base + RTIWWDSIZECTRL);
- 
- 	readl_relaxed(wdt->base + RTIWWDSIZECTRL);
-@@ -101,16 +109,53 @@ static int rti_wdt_ping(struct watchdog_device *wdd)
- 	/* put watchdog in active state */
- 	writel_relaxed(WDKEY_SEQ1, wdt->base + RTIWDKEY);
- 
--	if (readl_relaxed(wdt->base + RTIWDSTATUS))
--		WARN_ON_ONCE(1);
-+	return 0;
-+}
-+
-+static int rti_wdt_setup_hw_hb(struct watchdog_device *wdd, u32 wsize)
-+{
-+	/*
-+	 * RTI only supports a windowed mode, where the watchdog can only
-+	 * be petted during the open window; not too early or not too late.
-+	 * The HW configuration options only allow for the open window size
-+	 * to be 50% or less than that.
-+	 */
-+	switch (wsize) {
-+	case RTIWWDSIZE_50P:
-+		/* 50% open window => 50% min heartbeat */
-+		wdd->min_hw_heartbeat_ms = 500 * heartbeat;
-+		break;
-+
-+	case RTIWWDSIZE_25P:
-+		/* 25% open window => 75% min heartbeat */
-+		wdd->min_hw_heartbeat_ms = 750 * heartbeat;
-+		break;
-+
-+	case RTIWWDSIZE_12P5:
-+		/* 12.5% open window => 87.5% min heartbeat */
-+		wdd->min_hw_heartbeat_ms = 875 * heartbeat;
-+		break;
-+
-+	case RTIWWDSIZE_6P25:
-+		/* 6.5% open window => 93.5% min heartbeat */
-+		wdd->min_hw_heartbeat_ms = 935 * heartbeat;
-+		break;
-+
-+	case RTIWWDSIZE_3P125:
-+		/* 3.125% open window => 96.9% min heartbeat */
-+		wdd->min_hw_heartbeat_ms = 969 * heartbeat;
-+		break;
-+
-+	default:
-+		return -EINVAL;
-+	}
- 
- 	return 0;
- }
- 
--static unsigned int rti_wdt_get_timeleft(struct watchdog_device *wdd)
-+static unsigned int rti_wdt_get_timeleft_ms(struct watchdog_device *wdd)
- {
- 	u64 timer_counter;
--	unsigned long freq;
- 	u32 val;
- 	struct rti_wdt_device *wdt = watchdog_get_drvdata(wdd);
- 
-@@ -119,17 +164,20 @@ static unsigned int rti_wdt_get_timeleft(struct watchdog_device *wdd)
- 	if (val & DWDST)
- 		return 0;
- 
--	freq = clk_get_rate(wdt->clk);
--	if (!freq)
--		return 0;
--
- 	timer_counter = readl_relaxed(wdt->base + RTIDWDCNTR);
- 
--	do_div(timer_counter, freq);
-+	timer_counter *= 1000;
-+
-+	do_div(timer_counter, wdt->freq);
- 
- 	return timer_counter;
- }
- 
-+static unsigned int rti_wdt_get_timeleft(struct watchdog_device *wdd)
-+{
-+	return rti_wdt_get_timeleft_ms(wdd) / 1000;
-+}
-+
- static const struct watchdog_info rti_wdt_info = {
- 	.options = WDIOF_KEEPALIVEPING,
- 	.identity = "K3 RTI Watchdog",
-@@ -149,23 +197,43 @@ static int rti_wdt_probe(struct platform_device *pdev)
- 	struct resource *wdt_mem;
- 	struct watchdog_device *wdd;
- 	struct rti_wdt_device *wdt;
-+	struct clk *clk;
-+	u32 last_ping = 0;
- 
- 	wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
- 	if (!wdt)
- 		return -ENOMEM;
- 
--	wdt->clk = devm_clk_get(dev, NULL);
--	if (IS_ERR(wdt->clk)) {
--		if (PTR_ERR(wdt->clk) != -EPROBE_DEFER)
-+	clk = clk_get(dev, NULL);
-+	if (IS_ERR(clk)) {
-+		if (PTR_ERR(clk) != -EPROBE_DEFER)
- 			dev_err(dev, "failed to get clock\n");
--		return PTR_ERR(wdt->clk);
-+		return PTR_ERR(clk);
-+	}
-+
-+	wdt->freq = clk_get_rate(clk);
-+
-+	clk_put(clk);
-+
-+	if (!wdt->freq) {
-+		dev_err(dev, "Failed to get fck rate.\n");
-+		return -EINVAL;
- 	}
- 
-+	/*
-+	 * If watchdog is running at 32k clock, it is not accurate.
-+	 * Adjust frequency down in this case so that we don't pet
-+	 * the watchdog too often.
-+	 */
-+	if (wdt->freq < 32768)
-+		wdt->freq = wdt->freq * 9 / 10;
-+
- 	pm_runtime_enable(dev);
- 	ret = pm_runtime_get_sync(dev);
- 	if (ret) {
-+		pm_runtime_put_noidle(dev);
- 		if (ret != -EPROBE_DEFER)
--			dev_err(&pdev->dev, "runtime pm failed\n");
-+			dev_err(dev, "runtime pm failed\n");
- 		return ret;
- 	}
- 
-@@ -175,18 +243,10 @@ static int rti_wdt_probe(struct platform_device *pdev)
- 	wdd->info = &rti_wdt_info;
- 	wdd->ops = &rti_wdt_ops;
- 	wdd->min_timeout = 1;
--	/* Set min heartbeat to 1.1x window size */
--	wdd->min_hw_heartbeat_ms = 11 * DEFAULT_HEARTBEAT * 1000 / 20;
--	wdd->max_hw_heartbeat_ms = MAX_HEARTBEAT * 1000;
--	wdd->timeout = DEFAULT_HEARTBEAT;
-+	wdd->max_hw_heartbeat_ms = (WDT_PRELOAD_MAX << WDT_PRELOAD_SHIFT) /
-+		wdt->freq * 1000;
- 	wdd->parent = dev;
- 
--	set_bit(WDOG_RESET_KEEPALIVE, &wdd->status);
--
--	watchdog_init_timeout(wdd, heartbeat, dev);
--
--	dev_info(dev, "heartbeat %d sec\n", wdd->timeout);
--
- 	watchdog_set_drvdata(wdd, wdt);
- 	watchdog_set_nowayout(wdd, 1);
- 	watchdog_set_restart_priority(wdd, 128);
-@@ -198,16 +258,53 @@ static int rti_wdt_probe(struct platform_device *pdev)
- 		goto err_iomap;
- 	}
- 
-+	if (readl(wdt->base + RTIDWDCTRL) == WDENABLE_KEY) {
-+		u32 time_left_ms;
-+		u64 heartbeat_ms;
-+		u32 wsize;
-+
-+		set_bit(WDOG_HW_RUNNING, &wdd->status);
-+		time_left_ms = rti_wdt_get_timeleft_ms(wdd);
-+		heartbeat_ms = readl(wdt->base + RTIDWDPRLD);
-+		heartbeat_ms <<= WDT_PRELOAD_SHIFT;
-+		heartbeat_ms *= 1000;
-+		do_div(heartbeat_ms, wdt->freq);
-+		if (heartbeat_ms != heartbeat * 1000)
-+			dev_warn(dev, "watchdog already running, ignoring heartbeat config!\n");
-+
-+		heartbeat = heartbeat_ms;
-+		heartbeat /= 1000;
-+
-+		wsize = readl(wdt->base + RTIWWDSIZECTRL);
-+		ret = rti_wdt_setup_hw_hb(wdd, wsize);
-+		if (ret) {
-+			dev_err(dev, "bad window size.\n");
-+			goto err_iomap;
-+		}
-+
-+		last_ping = heartbeat_ms - time_left_ms;
-+		if (time_left_ms > heartbeat_ms) {
-+			dev_warn(dev, "time_left > heartbeat? Assuming last ping just before now.\n");
-+			last_ping = 0;
-+		}
-+	}
-+
-+	watchdog_init_timeout(wdd, heartbeat, dev);
-+
- 	ret = watchdog_register_device(wdd);
- 	if (ret) {
- 		dev_err(dev, "cannot register watchdog device\n");
- 		goto err_iomap;
- 	}
- 
-+	if (last_ping)
-+		watchdog_set_last_hw_keepalive(wdd, last_ping);
-+
- 	return 0;
- 
- err_iomap:
- 	pm_runtime_put_sync(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
- 
- 	return ret;
- }
-@@ -218,12 +315,13 @@ static int rti_wdt_remove(struct platform_device *pdev)
- 
- 	watchdog_unregister_device(&wdt->wdd);
- 	pm_runtime_put(&pdev->dev);
-+	pm_runtime_disable(&pdev->dev);
- 
- 	return 0;
- }
- 
- static const struct of_device_id rti_wdt_of_match[] = {
--	{ .compatible = "ti,rti-wdt", },
-+	{ .compatible = "ti,j7-rti-wdt", },
- 	{},
- };
- MODULE_DEVICE_TABLE(of, rti_wdt_of_match);
--- 
-2.31.1
-

board/PSG/iot2050/files/0026-arm64-dts-ti-k3-am65-mcu-Switch-to-upstream-watchdog.patch

@@ -1,35 +0,0 @@
-From 3fe9f4428ae8c4a8772218b7abf30b1e642b5b2c Mon Sep 17 00:00:00 2001
-From: Jan Kiszka <jan.kiszka@siemens.com>
-Date: Fri, 30 Jul 2021 08:59:18 +0200
-Subject: [PATCH 26/26] arm64: dts: ti: k3-am65-mcu: Switch to upstream
- watchdog
-
-Bind to the backported rti_wdt, rather than the legacy SDK version. Also
-enable shared power control.  This is needed when k3-rti-wdt is used as
-firmware and locked the power control for this IP block.
-
-Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
----
- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
-index 450456460182..605be5abea81 100644
---- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
-+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
-@@ -441,10 +441,10 @@
- 	};
- 
- 	mcu_rti1: rti@40610000 {
--		compatible = "ti,keystone-wdt";
-+		compatible = "ti,j7-rti-wdt";
- 		reg = <0x0 0x40610000 0x0 0x100>;
- 		clocks = <&k3_clks 135 0>;
--		power-domains = <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
-+		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
- 		assigned-clocks = <&k3_clks 135 0>;
- 		assigned-clock-parents = <&k3_clks 135 4>;
- 	};
--- 
-2.31.1
-

board/PSG/iot2050/files/iot2050-rt.cfg

@@ -3,8 +3,7 @@
 ##################################################
 
 CONFIG_PREEMPT=y
-CONFIG_PREEMPT_RT_BASE=y
-CONFIG_PREEMPT_RT_FULL=y 
+CONFIG_PREEMPT_RT=y
 
 #Disable PM features
 CONFIG_CPU_IDLE=n

board/PSG/iot2050/files/iot2050-upstream.cfg

@@ -1,10 +0,0 @@
-# Upstream kernel configs, to-be-merged into base defconfig eventually
-CONFIG_PCI_KEYSTONE_HOST=y
-CONFIG_K3_RTI_WATCHDOG=y
-CONFIG_TI_K3_RINGACC=y
-CONFIG_TI_K3_UDMA=y
-CONFIG_TI_K3_UDMA_GLUE_LAYER=y
-CONFIG_TI_PRUSS_INTC=m
-CONFIG_REMOTEPROC=y
-CONFIG_PRU_REMOTEPROC=m
-CONFIG_TI_ICSSG_PRUETH=m

board/PSG/iot2050/files/iot2050_defconfig_base

@@ -13,7 +13,6 @@ CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_MEMCG=y
-CONFIG_MEMCG_SWAP=y
 CONFIG_BLK_CGROUP=y
 CONFIG_CFS_BANDWIDTH=y
 CONFIG_CGROUP_PIDS=y
@@ -34,34 +33,18 @@ CONFIG_PERF_EVENTS=y
 # CONFIG_SLUB_DEBUG is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_ARCH_K3=y
-CONFIG_PCI=y
-CONFIG_PCI_IOV=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_PCIE_CADENCE_HOST=y
-CONFIG_PCIE_CADENCE_EP=y
-CONFIG_PCI_J721E=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_HOST_THUNDER_PEM=y
-CONFIG_PCI_HOST_THUNDER_ECAM=y
-CONFIG_PCI_KEYSTONE=y
-CONFIG_PCI_KEYSTONE_EP=y
-CONFIG_PCI_ENDPOINT=y
-CONFIG_PCI_ENDPOINT_CONFIGFS=y
-CONFIG_PCI_EPF_TEST=y
 # CONFIG_CAVIUM_ERRATUM_22375 is not set
 # CONFIG_CAVIUM_ERRATUM_23154 is not set
 # CONFIG_CAVIUM_ERRATUM_27456 is not set
 # CONFIG_CAVIUM_ERRATUM_30115 is not set
+# CONFIG_HISILICON_ERRATUM_161600802 is not set
 # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
 # CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
 # CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
-# CONFIG_HISILICON_ERRATUM_161600802 is not set
 # CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
 CONFIG_ARM64_VA_BITS_48=y
 CONFIG_SCHED_MC=y
-CONFIG_SECCOMP=y
 CONFIG_KEXEC=y
-# CONFIG_EFI is not set
 CONFIG_COMPAT=y
 CONFIG_HIBERNATION=y
 CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
@@ -71,21 +54,8 @@ CONFIG_CPU_FREQ_GOV_POWERSAVE=m
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
 CONFIG_CPUFREQ_DT=y
 CONFIG_VIRTUALIZATION=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512_ARM64_CE=m
-CONFIG_CRYPTO_SHA3_ARM64=m
-CONFIG_CRYPTO_SM3_ARM64_CE=m
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
-CONFIG_CRYPTO_CRC32_ARM64_CE=m
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_CHACHA20_NEON=m
-CONFIG_CRYPTO_AES_ARM64_BS=m
 CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_FORCE_LOAD=y
@@ -111,9 +81,6 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_INET_AH=m
 CONFIG_INET_ESP=m
 CONFIG_INET_IPCOMP=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
 CONFIG_IPV6=m
 CONFIG_INET6_AH=m
 CONFIG_INET6_IPCOMP=m
@@ -234,8 +201,7 @@ CONFIG_NET_ACT_PEDIT=m
 CONFIG_NET_ACT_SIMP=m
 CONFIG_NET_ACT_SKBEDIT=m
 CONFIG_NET_ACT_CSUM=m
-CONFIG_NET_CLS_IND=y
-CONFIG_HSR_PRP=y
+CONFIG_NET_SWITCHDEV=y
 CONFIG_BPF_JIT=y
 CONFIG_CAN=m
 CONFIG_CAN_C_CAN=m
@@ -243,7 +209,6 @@ CONFIG_CAN_C_CAN_PLATFORM=m
 CONFIG_CAN_M_CAN=m
 CONFIG_BT=m
 CONFIG_BT_HIDP=m
-# CONFIG_BT_HS is not set
 # CONFIG_BT_LE is not set
 CONFIG_BT_LEDS=y
 # CONFIG_BT_DEBUGFS is not set
@@ -257,22 +222,26 @@ CONFIG_MAC80211=m
 CONFIG_RFKILL=m
 CONFIG_NET_9P=y
 CONFIG_NET_9P_VIRTIO=y
-CONFIG_RPMSG_PROTO=m
+CONFIG_PCI=y
+CONFIG_PCI_IOV=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_HOST_THUNDER_PEM=y
+CONFIG_PCI_HOST_THUNDER_ECAM=y
+CONFIG_PCI_KEYSTONE_HOST=y
+CONFIG_PCI_KEYSTONE_EP=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_CMA=y
-CONFIG_CMA_SIZE_MBYTES=24
 CONFIG_SIMPLE_PM_BUS=y
 CONFIG_MTD=y
 CONFIG_MTD_TESTS=m
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_DENALI_DT=y
 CONFIG_MTD_SPI_NOR=y
 # CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_MTD_UBI=y
 CONFIG_MTD_HYPERBUS=y
 CONFIG_HBMC_AM654=y
@@ -290,12 +259,11 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_SAS_ATA=y
 CONFIG_SCSI_HISI_SAS=m
-CONFIG_SCSI_HISI_SAS_PCI=m
 CONFIG_SCSI_UFSHCD=y
 CONFIG_SCSI_UFSHCD_PLATFORM=y
 CONFIG_SCSI_UFS_CDNS_PLATFORM=y
-CONFIG_SCSI_UFS_BSG=y
 CONFIG_SCSI_UFS_TI_J721E=y
+CONFIG_SCSI_UFS_BSG=y
 CONFIG_ATA=m
 CONFIG_SATA_AHCI=m
 CONFIG_SATA_AHCI_PLATFORM=m
@@ -333,7 +301,6 @@ CONFIG_MACB=y
 # CONFIG_NET_VENDOR_EMULEX is not set
 # CONFIG_NET_VENDOR_EZCHIP is not set
 # CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_HP is not set
 # CONFIG_NET_VENDOR_I825XX is not set
 CONFIG_E1000=m
 CONFIG_E1000E=m
@@ -363,20 +330,18 @@ CONFIG_SMSC911X=y
 # CONFIG_NET_VENDOR_SUN is not set
 # CONFIG_NET_VENDOR_SYNOPSYS is not set
 # CONFIG_NET_VENDOR_TEHUTI is not set
-CONFIG_TI_AM65_CPSW_NUSS=y
-CONFIG_TI_PRUETH=m
 CONFIG_TI_ICSSG_PRUETH=m
 # CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_MDIO_BUS_MUX_MMIOREG=y
-CONFIG_AT803X_PHY=m
-CONFIG_DP83848_PHY=y
-CONFIG_DP83867_PHY=y
 CONFIG_MARVELL_PHY=y
 CONFIG_MARVELL_10G_PHY=m
 CONFIG_MICREL_PHY=y
+CONFIG_AT803X_PHY=m
 CONFIG_REALTEK_PHY=m
 CONFIG_ROCKCHIP_PHY=y
+CONFIG_DP83848_PHY=y
+CONFIG_DP83867_PHY=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
 CONFIG_USB_PEGASUS=m
 CONFIG_USB_RTL8150=m
 CONFIG_USB_RTL8152=m
@@ -403,7 +368,6 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_ADC=m
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_MATRIX=m
-CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=m
 CONFIG_TOUCHSCREEN_GOODIX=m
@@ -430,8 +394,8 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_OMAP=y
-CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SPI=y
+CONFIG_SPI_CADENCE_QUADSPI=y
 CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_PL022=y
 CONFIG_SPMI=y
@@ -452,7 +416,6 @@ CONFIG_GPIO_TPIC2810=m
 CONFIG_GPIO_MAX77620=y
 CONFIG_GPIO_PISOSR=m
 CONFIG_W1=m
-CONFIG_POWER_AVS=y
 CONFIG_POWER_RESET_XGENE=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_SYSCON_REBOOT_MODE=y
@@ -460,7 +423,6 @@ CONFIG_BATTERY_SBS=m
 CONFIG_BATTERY_BQ27XXX=y
 CONFIG_SENSORS_LM90=m
 CONFIG_SENSORS_INA2XX=m
-CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
 CONFIG_CPU_THERMAL=y
 CONFIG_THERMAL_EMULATION=y
 CONFIG_K3_THERMAL=y
@@ -468,8 +430,6 @@ CONFIG_WATCHDOG=y
 CONFIG_ARM_SP805_WATCHDOG=y
 CONFIG_K3_RTI_WATCHDOG=y
 CONFIG_MFD_BD9571MWV=y
-CONFIG_MFD_CROS_EC=y
-CONFIG_MFD_CROS_EC_CHARDEV=m
 CONFIG_MFD_HI6421_PMIC=y
 CONFIG_MFD_MAX77620=y
 CONFIG_MFD_RK808=y
@@ -493,30 +453,19 @@ CONFIG_RC_CORE=m
 CONFIG_RC_DECODERS=y
 CONFIG_RC_DEVICES=y
 CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
 # CONFIG_DVB_NET is not set
 CONFIG_MEDIA_USB_SUPPORT=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_VIDEO_TI_CAL=m
 CONFIG_V4L_MEM2MEM_DRIVERS=y
-CONFIG_VIDEO_IMG_VXD_DEC=m
-# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
 CONFIG_VIDEO_OV2659=m
 CONFIG_VIDEO_OV5640=m
-CONFIG_VIDEO_OV1063X=m
-CONFIG_VIDEO_OV490=m
-CONFIG_VIDEO_MT9T11X=m
 # CONFIG_VGA_ARB is not set
 CONFIG_DRM=y
 CONFIG_DRM_I2C_NXP_TDA998X=y
 CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS=y
-CONFIG_DRM_CDNS_MHDP=m
 CONFIG_DRM_SII902X=y
 CONFIG_DRM_TOSHIBA_TC358767=y
 CONFIG_DRM_TOSHIBA_TC358768=y
@@ -524,8 +473,6 @@ CONFIG_DRM_TI_TFP410=y
 CONFIG_DRM_TIDSS=y
 CONFIG_DRM_LEGACY=y
 CONFIG_FB_SSD1307=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_GENERIC=m
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_BACKLIGHT_LP855X=m
 CONFIG_BACKLIGHT_GPIO=y
@@ -545,11 +492,10 @@ CONFIG_SND_SOC_PCM3168A_I2C=m
 CONFIG_SND_SOC_TLV320AIC31XX=m
 CONFIG_SND_SOC_TLV320AIC3X=m
 CONFIG_SND_SIMPLE_CARD=m
-CONFIG_SND_SIMPLE_SCU_CARD=m
 CONFIG_SND_AUDIO_GRAPH_CARD=m
-CONFIG_SND_AUDIO_GRAPH_SCU_CARD=m
 CONFIG_HID_MULTITOUCH=m
 CONFIG_I2C_HID=m
+CONFIG_USB_ULPI_BUS=y
 CONFIG_USB=m
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_OTG=y
@@ -615,7 +561,6 @@ CONFIG_USB_G_MULTI_CDC=y
 CONFIG_USB_G_HID=m
 CONFIG_USB_G_DBGP=m
 CONFIG_USB_G_WEBCAM=m
-CONFIG_USB_ULPI_BUS=y
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_ARMMMCI=y
@@ -645,13 +590,14 @@ CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_RK808=m
 CONFIG_RTC_DRV_S5M=y
 CONFIG_RTC_DRV_DS3232=y
-CONFIG_RTC_DRV_CROS_EC=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_DMADEVICES=y
 CONFIG_MV_XOR_V2=y
 CONFIG_PL330_DMA=y
 CONFIG_QCOM_HIDMA_MGMT=y
 CONFIG_QCOM_HIDMA=y
+CONFIG_TI_K3_UDMA=y
+CONFIG_TI_K3_UDMA_GLUE_LAYER=y
 CONFIG_VFIO=y
 CONFIG_VFIO_PCI=y
 CONFIG_VIRTIO_PCI=y
@@ -660,11 +606,6 @@ CONFIG_VIRTIO_MMIO=y
 CONFIG_STAGING=y
 CONFIG_ION=y
 CONFIG_ION_SYSTEM_HEAP=y
-CONFIG_ION_CARVEOUT_HEAP=y
-CONFIG_ION_CHUNK_HEAP=y
-CONFIG_ION_TI=y
-CONFIG_CROS_EC_I2C=y
-CONFIG_CROS_EC_SPI=y
 CONFIG_COMMON_CLK_RK808=y
 CONFIG_COMMON_CLK_CS2000_CP=y
 CONFIG_COMMON_CLK_S2MPS11=y
@@ -676,37 +617,27 @@ CONFIG_HWSPINLOCK_OMAP=y
 CONFIG_OMAP2PLUS_MBOX=y
 CONFIG_ARM_SMMU=y
 CONFIG_ARM_SMMU_V3=y
-CONFIG_REMOTEPROC=m
-CONFIG_TI_K3_R5_REMOTEPROC=m
+CONFIG_REMOTEPROC=y
 CONFIG_TI_K3_DSP_REMOTEPROC=m
+CONFIG_TI_K3_R5_REMOTEPROC=m
 CONFIG_RPMSG_QCOM_GLINK_RPM=y
 CONFIG_RPMSG_VIRTIO=m
-CONFIG_RPMSG_PRU=m
-CONFIG_RPMSG_KDRV_DISPLAY=y
 CONFIG_ARCH_K3_AM6_SOC=y
 CONFIG_ARCH_K3_J721E_SOC=y
-CONFIG_SOC_TI=y
 CONFIG_TI_SCI_PM_DOMAINS=y
 CONFIG_TI_PRUSS=m
-CONFIG_TI_K3_UDMA_DESC_POOL=y
 CONFIG_EXTCON_PALMAS=m
 CONFIG_EXTCON_USB_GPIO=m
-CONFIG_EXTCON_USBC_CROS_EC=y
 CONFIG_MEMORY=y
 CONFIG_IIO=y
 CONFIG_TI_AM335X_ADC=m
-CONFIG_IIO_CROS_EC_SENSORS_CORE=m
-CONFIG_IIO_CROS_EC_SENSORS=m
-CONFIG_IIO_CROS_EC_LIGHT_PROX=m
-CONFIG_IIO_CROS_EC_BARO=m
-CONFIG_PWM_CROS_EC=m
 CONFIG_PWM_TIECAP=y
 CONFIG_PWM_TIEHRPWM=y
+CONFIG_TI_PRUSS_INTC=m
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_TI_SCI=y
 CONFIG_RESET_TI_SYSCON=y
 CONFIG_PHY_XGENE=y
-CONFIG_PHY_CADENCE_DP=y
 CONFIG_PHY_CADENCE_SIERRA=y
 CONFIG_PHY_QCOM_USB_HS=y
 CONFIG_PHY_AM654_SERDES=y
@@ -741,7 +672,6 @@ CONFIG_ROOT_NFS=y
 CONFIG_CIFS=m
 CONFIG_CIFS_XATTR=y
 CONFIG_CIFS_POSIX=y
-CONFIG_CIFS_ACL=y
 CONFIG_9P_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
@@ -749,13 +679,15 @@ CONFIG_SECURITY=y
 CONFIG_CRYPTO_TEST=m
 CONFIG_CRYPTO_ECHAINIV=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=24
 CONFIG_PRINTK_TIME=y
-CONFIG_DEBUG_FS=y
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
 CONFIG_SCHEDSTATS=y
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
-CONFIG_MEMTEST=y
 CONFIG_SAMPLES=y
 CONFIG_SAMPLE_RPMSG_CLIENT=m
-CONFIG_INPUT_UINPUT=y
+CONFIG_MEMTEST=y
+CONFIG_TI_DAVINCI_MDIO=y

board/PSG/iot2050/files/iot2050_defconfig_extra.cfg

@@ -160,6 +160,7 @@ CONFIG_NFT_REJECT_IPV6=m
 CONFIG_NF_TABLES_IPV6=y
 CONFIG_NF_REJECT_IPV6=m
 CONFIG_NF_LOG_IPV6=m
+CONFIG_BRIDGE_NETFILTER=m
 CONFIG_NETFILTER_XTABLES=m
 CONFIG_NETFILTER_XT_NAT=m
 CONFIG_NETFILTER_XT_TARGET_LOG=m
@@ -185,3 +186,14 @@ CONFIG_NET_CLS_POLICE=y
 CONFIG_USB_NET_QMI_WWAN=m
 CONFIG_USB_NET_HUAWEI_CDC_NCM=m
 CONFIG_USB_NET_CDC_MBIM=m
+
+CONFIG_BPF_SYSCALL=y
+CONFIG_CGROUP_BPF=y
+
+CONFIG_WIREGUARD=m
+
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_OVERLAY_FS=y
+CONFIG_DM_VERITY=y
+CONFIG_DM_CRYPT=y

board/PSG/iot2050/files/patches-5.10/0001-dmaengine-ti-k3-udma-glue-Add-function-to-get-device.patch

@@ -0,0 +1,100 @@
+From 3f592d3a8794d4db3192b71a7f8df363cb1c2c62 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Tue, 8 Dec 2020 11:04:24 +0200
+Subject: [PATCH] dmaengine: ti: k3-udma-glue: Add function to get device
+ pointer for DMA API
+
+Glue layer users should use the device of the DMA for DMA mapping and
+allocations as it is the DMA which accesses to descriptors and buffers,
+not the clients
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Link: https://lore.kernel.org/r/20201208090440.31792-5-peter.ujfalusi@ti.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/dma/ti/k3-udma-glue.c    | 14 ++++++++++++++
+ drivers/dma/ti/k3-udma-private.c |  6 ++++++
+ drivers/dma/ti/k3-udma.h         |  1 +
+ include/linux/dma/k3-udma-glue.h |  4 ++++
+ 4 files changed, 25 insertions(+)
+
+diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c
+index a367584f0d7b..a53bc4707ae8 100644
+--- a/drivers/dma/ti/k3-udma-glue.c
++++ b/drivers/dma/ti/k3-udma-glue.c
+@@ -487,6 +487,13 @@ int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn)
+ }
+ EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_irq);
+ 
++struct device *
++	k3_udma_glue_tx_get_dma_device(struct k3_udma_glue_tx_channel *tx_chn)
++{
++	return xudma_get_device(tx_chn->common.udmax);
++}
++EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_dma_device);
++
+ static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn)
+ {
+ 	const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm;
+@@ -1189,3 +1196,10 @@ int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
+ 	return flow->virq;
+ }
+ EXPORT_SYMBOL_GPL(k3_udma_glue_rx_get_irq);
++
++struct device *
++	k3_udma_glue_rx_get_dma_device(struct k3_udma_glue_rx_channel *rx_chn)
++{
++	return xudma_get_device(rx_chn->common.udmax);
++}
++EXPORT_SYMBOL_GPL(k3_udma_glue_rx_get_dma_device);
+diff --git a/drivers/dma/ti/k3-udma-private.c b/drivers/dma/ti/k3-udma-private.c
+index dadab2feca08..bae6150b1d8d 100644
+--- a/drivers/dma/ti/k3-udma-private.c
++++ b/drivers/dma/ti/k3-udma-private.c
+@@ -50,6 +50,12 @@ struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property)
+ }
+ EXPORT_SYMBOL(of_xudma_dev_get);
+ 
++struct device *xudma_get_device(struct udma_dev *ud)
++{
++	return ud->dev;
++}
++EXPORT_SYMBOL(xudma_get_device);
++
+ u32 xudma_dev_get_psil_base(struct udma_dev *ud)
+ {
+ 	return ud->psil_base;
+diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
+index 09c4529e013d..d1cace0cb43b 100644
+--- a/drivers/dma/ti/k3-udma.h
++++ b/drivers/dma/ti/k3-udma.h
+@@ -112,6 +112,7 @@ int xudma_navss_psil_unpair(struct udma_dev *ud, u32 src_thread,
+ 			    u32 dst_thread);
+ 
+ struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property);
++struct device *xudma_get_device(struct udma_dev *ud);
+ void xudma_dev_put(struct udma_dev *ud);
+ u32 xudma_dev_get_psil_base(struct udma_dev *ud);
+ struct udma_tisci_rm *xudma_dev_get_tisci_rm(struct udma_dev *ud);
+diff --git a/include/linux/dma/k3-udma-glue.h b/include/linux/dma/k3-udma-glue.h
+index 5eb34ad973a7..d7c12f31377c 100644
+--- a/include/linux/dma/k3-udma-glue.h
++++ b/include/linux/dma/k3-udma-glue.h
+@@ -41,6 +41,8 @@ void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
+ u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn);
+ u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn);
+ int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn);
++struct device *
++	k3_udma_glue_tx_get_dma_device(struct k3_udma_glue_tx_channel *tx_chn);
+ 
+ enum {
+ 	K3_UDMA_GLUE_SRC_TAG_LO_KEEP = 0,
+@@ -130,5 +132,7 @@ int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
+ 				u32 flow_idx);
+ int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
+ 				 u32 flow_idx);
++struct device *
++	k3_udma_glue_rx_get_dma_device(struct k3_udma_glue_rx_channel *rx_chn);
+ 
+ #endif /* K3_UDMA_GLUE_H_ */

board/PSG/iot2050/files/patches-5.10/0002-arm64-dts-ti-k3-am65-ringacc-drop-ti-dma-ring-reset-.patch

@@ -0,0 +1,40 @@
+From bcc2ccf02444bd6a99c812e9000388d1b65aa127 Mon Sep 17 00:00:00 2001
+From: Grygorii Strashko <grygorii.strashko@ti.com>
+Date: Sat, 29 Aug 2020 21:41:39 +0300
+Subject: [PATCH] arm64: dts: ti: k3-am65: ringacc: drop ti,
+ dma-ring-reset-quirk
+
+Remove obsolete "ti,dma-ring-reset-quirk" Ringacc DT property.
+
+Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/20200829184139.15547-4-grygorii.strashko@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 -
+ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 1 -
+ 2 files changed, 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index d04189771c77..344c81ff31e9 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -615,7 +615,6 @@ ringacc: ringacc@3c000000 {
+ 			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ 			ti,num-rings = <818>;
+ 			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+-			ti,dma-ring-reset-quirk;
+ 			ti,sci = <&dmsc>;
+ 			ti,sci-dev-id = <187>;
+ 			msi-parent = <&inta_main_udmass>;
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+index 29aaf8dca6f6..044042b166d9 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+@@ -135,7 +135,6 @@ mcu_ringacc: ringacc@2b800000 {
+ 			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
+ 			ti,num-rings = <286>;
+ 			ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
+-			ti,dma-ring-reset-quirk;
+ 			ti,sci = <&dmsc>;
+ 			ti,sci-dev-id = <195>;
+ 			msi-parent = <&inta_main_udmass>;

board/PSG/iot2050/files/patches-5.10/0003-arm64-dts-ti-k3-am65-mcu-Add-MCU-domain-R5F-cluster-.patch

@@ -0,0 +1,95 @@
+From f01a195249b904d867e63d27b4f4c88f28b2b78e Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Wed, 28 Oct 2020 22:37:55 -0500
+Subject: [PATCH] arm64: dts: ti: k3-am65-mcu: Add MCU domain R5F cluster node
+
+The AM65x SoCs have a single dual-core Arm Cortex-R5F processor (R5FSS)
+subsystem/cluster. This R5F cluster (MCU_R5FSS0) is present within the
+MCU domain, and can be configured at boot time to be either run in a
+LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in
+Split-mode. This subsystem has 64 KB each Tightly-Coupled Memory (TCM)
+internal memories for each core split between two banks - TCMA and TCMB
+(further interleaved into two banks). There are some IP integration
+differences from standard Arm R5F clusters such as the absence of an ACP
+port, presence of an additional TI-specific Region Address Translater
+(RAT) module for translating 32-bit CPU addresses into larger system
+bus addresses etc.
+
+Add the DT node for this R5F cluster/subsystem, the two R5F cores are
+added as child nodes to the main cluster node. The cluster is configured
+to run in LockStep mode by default, with the ATCMs enabled to allow the
+R5 cores to execute code from DDR with boot-strapping code from ATCM.
+The inter-processor communication between the main A53 cores and these
+processors is achieved through shared memory and Mailboxes.
+
+The following firmware names are used by default for these cores, and
+can be overridden in a board dts file if needed:
+    am65x-mcu-r5f0_0-fw (LockStep mode and for Core0 in Split mode)
+    am65x-mcu-r5f0_1-fw (Core1 in Split mode)
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
+Link: https://lore.kernel.org/r/20201029033802.15366-2-s-anna@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 42 ++++++++++++++++++++++++-
+ 1 file changed, 41 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+index 044042b166d9..7454c8cec0cc 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+@@ -2,7 +2,7 @@
+ /*
+  * Device Tree Source for AM6 SoC Family MCU Domain peripherals
+  *
+- * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
++ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/
+  */
+ 
+ &cbass_mcu {
+@@ -268,4 +268,44 @@ mcu_cpsw_cpts_mux: refclk-mux {
+ 			};
+ 		};
+ 	};
++
++	mcu_r5fss0: r5fss@41000000 {
++		compatible = "ti,am654-r5fss";
++		ti,cluster-mode = <1>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <0x41000000 0x00 0x41000000 0x20000>,
++			 <0x41400000 0x00 0x41400000 0x20000>;
++		power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>;
++
++		mcu_r5fss0_core0: r5f@41000000 {
++			compatible = "ti,am654-r5f";
++			reg = <0x41000000 0x00008000>,
++			      <0x41010000 0x00008000>;
++			reg-names = "atcm", "btcm";
++			ti,sci = <&dmsc>;
++			ti,sci-dev-id = <159>;
++			ti,sci-proc-ids = <0x01 0xff>;
++			resets = <&k3_reset 159 1>;
++			firmware-name = "am65x-mcu-r5f0_0-fw";
++			ti,atcm-enable = <1>;
++			ti,btcm-enable = <1>;
++			ti,loczrama = <1>;
++		};
++
++		mcu_r5fss0_core1: r5f@41400000 {
++			compatible = "ti,am654-r5f";
++			reg = <0x41400000 0x00008000>,
++			      <0x41410000 0x00008000>;
++			reg-names = "atcm", "btcm";
++			ti,sci = <&dmsc>;
++			ti,sci-dev-id = <245>;
++			ti,sci-proc-ids = <0x02 0xff>;
++			resets = <&k3_reset 245 1>;
++			firmware-name = "am65x-mcu-r5f0_1-fw";
++			ti,atcm-enable = <1>;
++			ti,btcm-enable = <1>;
++			ti,loczrama = <1>;
++		};
++	};
+ };

board/PSG/iot2050/files/patches-5.10/0004-arm64-dts-ti-k3-am65-Cleanup-disabled-nodes-at-SoC-d.patch

@@ -0,0 +1,122 @@
+From 4734cecbafdb6c2cfb9bd1f5e39515f1fe18f883 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Fri, 13 Nov 2020 15:18:22 -0600
+Subject: [PATCH] arm64: dts: ti: k3-am65*: Cleanup disabled nodes at SoC dtsi
+ level
+
+The device tree standard states that when the status property is
+not present under a node, the okay value is assumed. There are many
+reasons for doing the same, the number of strings in the device
+tree, default power management functionality, etc. are a few of the
+reasons.
+
+In general, after a few rounds of discussions [1] there are few
+options one could take when dealing with SoC dtsi and board dts
+
+a. SoC dtsi provide nodes as a super-set default (aka enabled) state and
+   to prevent messy board files, when more boards are added per SoC, we
+   optimize and disable commonly un-used nodes in board-common.dtsi
+b. SoC dtsi disables all hardware dependent nodes by default and board
+   dts files enable nodes based on a need basis.
+c. Subjectively pick and choose which nodes we will disable by default
+   in SoC dtsi and over the years we can optimize things and change
+   default state depending on the need.
+
+While there are pros and cons on each of these approaches, the right
+thing to do will be to stick with device tree default standards and
+work within those established rules. So, we choose to go with option
+(a).
+
+Lets cleanup defaults of am654 SoC dtsi before this gets more harder
+to cleanup later on and new SoCs are added.
+
+The dtb generated is identical with the patch and it is just cleanup to
+ensure we have a clean usage model
+
+NOTE: There is a known risk of omission that new board dts developers
+might miss reviewing both the board schematics in addition to all the
+DT nodes of the SoC when setting appropriate nodes status to disable
+or reserved in the board dts. This can expose issues in drivers that
+may not anticipate an incomplete node (example: missing appropriate
+board properties) being in an "okay" state. These cases are considered
+bugs and need to be fixed in the drivers as and when identified.
+
+[1] https://lore.kernel.org/linux-arm-kernel/20201027130701.GE5639@atomide.com/
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Reviewed-by: Tony Lindgren <tony@atomide.com>
+Cc: Jyri Sarha <jsarha@ti.com>
+Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Cc: Tony Lindgren <tony@atomide.com>
+Link: https://lore.kernel.org/r/20201113211826.13087-2-nm@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi       |  8 --------
+ arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 16 ++++++++++++++++
+ 2 files changed, 16 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index 344c81ff31e9..ee7b7c356f01 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -772,8 +772,6 @@ mcasp0: mcasp@2b00000 {
+ 		clocks = <&k3_clks 104 0>;
+ 		clock-names = "fck";
+ 		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+-
+-		status = "disabled";
+ 	};
+ 
+ 	mcasp1: mcasp@2b10000 {
+@@ -791,8 +789,6 @@ mcasp1: mcasp@2b10000 {
+ 		clocks = <&k3_clks 105 0>;
+ 		clock-names = "fck";
+ 		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+-
+-		status = "disabled";
+ 	};
+ 
+ 	mcasp2: mcasp@2b20000 {
+@@ -810,8 +806,6 @@ mcasp2: mcasp@2b20000 {
+ 		clocks = <&k3_clks 106 0>;
+ 		clock-names = "fck";
+ 		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+-
+-		status = "disabled";
+ 	};
+ 
+ 	cal: cal@6f03000 {
+@@ -867,8 +861,6 @@ dss: dss@4a00000 {
+ 
+ 		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ 
+-		status = "disabled";
+-
+ 		dma-coherent;
+ 
+ 		dss_ports: ports {
+diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+index 937dd7280c7a..8c082af489f5 100644
+--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
++++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+@@ -486,3 +486,19 @@ &cpsw_port1 {
+ 	phy-mode = "rgmii-rxid";
+ 	phy-handle = <&phy0>;
+ };
++
++&mcasp0 {
++	status = "disabled";
++};
++
++&mcasp1 {
++	status = "disabled";
++};
++
++&mcasp2 {
++	status = "disabled";
++};
++
++&dss {
++	status = "disabled";
++};

board/PSG/iot2050/files/patches-5.10/0005-arm64-dts-ti-am65-j721e-Fix-up-un-necessary-status-s.patch

@@ -0,0 +1,45 @@
+From 187ddbf1c2b3ad2e0c4dd755fe1e240a4c85564c Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Fri, 13 Nov 2020 15:18:24 -0600
+Subject: [PATCH] arm64: dts: ti: am65/j721e: Fix up un-necessary status set to
+ "okay" for crypto
+
+The default state of a device tree node is "okay". There is no specific
+use of explicitly adding status = "okay" in the SoC dtsi.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Tony Lindgren <tony@atomide.com>
+Reviewed-by: Keerthy <j-keerthy@ti.com>
+Acked-by: Tero Kristo <t-kristo@ti.com>
+Cc: Keerthy <j-keerthy@ti.com>
+Link: https://lore.kernel.org/r/20201113211826.13087-4-nm@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi  | 1 -
+ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 --
+ 2 files changed, 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index ee7b7c356f01..ba1529436128 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -122,7 +122,6 @@ crypto: crypto@4e00000 {
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+ 		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
+-		status = "okay";
+ 
+ 		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
+ 				<&main_udmap 0x4001>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+index 0350ddfe2c72..b8ca6e03de36 100644
+--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+@@ -362,8 +362,6 @@ main_crypto: crypto@4e00000 {
+ 		#size-cells = <2>;
+ 		ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
+ 
+-		status = "okay";
+-
+ 		dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
+ 				<&main_udmap 0x4001>;
+ 		dma-names = "tx", "rx1", "rx2";

board/PSG/iot2050/files/patches-5.10/0006-arm64-dts-ti-k3-mmc-fix-dtbs_check-warnings.patch

@@ -0,0 +1,130 @@
+From 57097d1701c3803790af02f8ee5fd828fc9153c4 Mon Sep 17 00:00:00 2001
+From: Grygorii Strashko <grygorii.strashko@ti.com>
+Date: Fri, 15 Jan 2021 21:30:16 +0200
+Subject: [PATCH] arm64: dts: ti: k3: mmc: fix dtbs_check warnings
+
+Now the dtbs_check produces below warnings
+ sdhci@4f80000: clock-names:0: 'clk_ahb' was expected
+ sdhci@4f80000: clock-names:1: 'clk_xin' was expected
+ $nodename:0: 'sdhci@4f80000' does not match '^mmc(@.*)?$'
+
+Fix above warnings by updating mmc DT definitions to follow
+sdhci-am654.yaml bindings:
+ - rename sdhci dt nodes to 'mmc@'
+ - swap clk_xin/clk_ahb clocks, the clk_ahb clock expected to be defined
+first
+
+Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Suman Anna <s-anna@ti.com>
+Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
+Link: https://lore.kernel.org/r/20210115193016.5581-1-grygorii.strashko@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi  |  4 ++--
+ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi |  8 ++++----
+ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 18 +++++++++---------
+ 3 files changed, 15 insertions(+), 15 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index ba1529436128..cf7656cf650e 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -259,7 +259,7 @@ main_spi4: spi@2140000 {
+ 		#size-cells = <0>;
+ 	};
+ 
+-	sdhci0: sdhci@4f80000 {
++	sdhci0: mmc@4f80000 {
+ 		compatible = "ti,am654-sdhci-5.1";
+ 		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
+ 		power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
+@@ -283,7 +283,7 @@ sdhci0: sdhci@4f80000 {
+ 		dma-coherent;
+ 	};
+ 
+-	sdhci1: sdhci@4fa0000 {
++	sdhci1: mmc@4fa0000 {
+ 		compatible = "ti,am654-sdhci-5.1";
+ 		reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
+ 		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+index bef47f96376d..cb22e65d61ab 100644
+--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+@@ -390,8 +390,8 @@ main_sdhci0: mmc@4f80000 {
+ 		reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
+ 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+-		clock-names = "clk_xin", "clk_ahb";
+-		clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
++		clock-names = "clk_ahb", "clk_xin";
++		clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
+ 		ti,otap-del-sel-legacy = <0x0>;
+ 		ti,otap-del-sel-mmc-hs = <0x0>;
+ 		ti,otap-del-sel-ddr52 = <0x6>;
+@@ -409,8 +409,8 @@ main_sdhci1: mmc@4fb0000 {
+ 		reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
+ 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+-		clock-names = "clk_xin", "clk_ahb";
+-		clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
++		clock-names = "clk_ahb", "clk_xin";
++		clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
+ 		ti,otap-del-sel-legacy = <0x0>;
+ 		ti,otap-del-sel-sd-hs = <0x0>;
+ 		ti,otap-del-sel-sdr12 = <0xf>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+index b8ca6e03de36..81fddd145b86 100644
+--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+@@ -1072,13 +1072,13 @@ main_gpio7: gpio@631000 {
+ 		clock-names = "gpio";
+ 	};
+ 
+-	main_sdhci0: sdhci@4f80000 {
++	main_sdhci0: mmc@4f80000 {
+ 		compatible = "ti,j721e-sdhci-8bit";
+ 		reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
+ 		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 		power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+-		clock-names = "clk_xin", "clk_ahb";
+-		clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
++		clock-names = "clk_ahb", "clk_xin";
++		clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
+ 		assigned-clocks = <&k3_clks 91 1>;
+ 		assigned-clock-parents = <&k3_clks 91 2>;
+ 		bus-width = <8>;
+@@ -1090,13 +1090,13 @@ main_sdhci0: sdhci@4f80000 {
+ 		dma-coherent;
+ 	};
+ 
+-	main_sdhci1: sdhci@4fb0000 {
++	main_sdhci1: mmc@4fb0000 {
+ 		compatible = "ti,j721e-sdhci-4bit";
+ 		reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
+ 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 		power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+-		clock-names = "clk_xin", "clk_ahb";
+-		clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
++		clock-names = "clk_ahb", "clk_xin";
++		clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
+ 		assigned-clocks = <&k3_clks 92 0>;
+ 		assigned-clock-parents = <&k3_clks 92 1>;
+ 		ti,otap-del-sel = <0x2>;
+@@ -1106,13 +1106,13 @@ main_sdhci1: sdhci@4fb0000 {
+ 		no-1-8-v;
+ 	};
+ 
+-	main_sdhci2: sdhci@4f98000 {
++	main_sdhci2: mmc@4f98000 {
+ 		compatible = "ti,j721e-sdhci-4bit";
+ 		reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
+ 		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ 		power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
+-		clock-names = "clk_xin", "clk_ahb";
+-		clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
++		clock-names = "clk_ahb", "clk_xin";
++		clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
+ 		assigned-clocks = <&k3_clks 93 0>;
+ 		assigned-clock-parents = <&k3_clks 93 1>;
+ 		ti,otap-del-sel = <0x2>;

board/PSG/iot2050/files/patches-5.10/0007-arm64-dts-ti-k3-am65-main-Add-device_type-to-pcie-_r.patch

@@ -0,0 +1,37 @@
+From c8be67df79ed8ed0735303ef58001d6a31a7dc75 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Thu, 11 Feb 2021 20:32:56 +0100
+Subject: [PATCH] arm64: dts: ti: k3-am65-main: Add device_type to pcie*_rc
+ nodes
+
+This is demanded by the parent binding of ti,am654-pcie-rc, see
+Documentation/devicetree/bindings/pci/designware-pcie.txt.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Kishon Vijay Abraham I <kishon@ti.com>
+Link: https://lore.kernel.org/r/881dfd6c75423efce1d10261909939cd5ef19937.1613071976.git.jan.kiszka@siemens.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index cf7656cf650e..3c36ae6d7816 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -709,6 +709,7 @@ pcie0_rc: pcie@5500000 {
+ 		dma-coherent;
+ 		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ 		msi-map = <0x0 &gic_its 0x0 0x10000>;
++		device_type = "pci";
+ 	};
+ 
+ 	pcie0_ep: pcie-ep@5500000 {
+@@ -741,6 +742,7 @@ pcie1_rc: pcie@5600000 {
+ 		dma-coherent;
+ 		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ 		msi-map = <0x0 &gic_its 0x10000 0x10000>;
++		device_type = "pci";
+ 	};
+ 
+ 	pcie1_ep: pcie-ep@5600000 {

board/PSG/iot2050/files/patches-5.10/0008-arm64-dts-ti-k3-am65-main-Add-ICSSG-nodes.patch

@@ -0,0 +1,476 @@
+From ad1e81b715bbd6ff4d11690bcfb0668d5e492177 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Thu, 4 Mar 2021 10:07:11 -0600
+Subject: [PATCH] arm64: dts: ti: k3-am65-main: Add ICSSG nodes
+
+Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems
+that are present on the K3 AM65x SoCs. The three ICSSGs are identical
+to each other for the most part, with the ICSSG2 supporting slightly
+enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance
+is represented by a PRUSS subsystem node. These nodes are enabled by
+default.
+
+The ICSSGs on K3 AM65x SoCs are super-sets of the PRUSS on the AM57xx/
+6AK2G SoCs except for larger Shared Data RAM and the lack of a PRU-ICSS
+crossbar. They include two auxiliary PRU cores called RTUs and few other
+additional sub-modules. The interrupt integration is also different on
+the K3 AM65x SoCs and are propagated through various SoC-level Interrupt
+Router and Interrupt Aggregator blocks. The AM65x SR2.0 SoCs have a
+revised ICSSG IP that is based off the subsequent IP used on J721E SoCs,
+and has two new auxiliary PRU cores called Tx_PRUs. The Tx_PRUs have 6 KB
+of IRAMs and leverage the same host interrupts as the regular PRU cores.
+The Broadside (BS) RAM within each core is also sized differently w.r.t
+SR1.0.
+
+The ICSSG subsystem node contains the entire address space. The various
+sub-modules of the ICSSG are represented as individual child nodes (so
+platform devices themselves) of the PRUSS subsystem node. These include
+the various PRU cores and the interrupt controller. All the Data RAMs
+are represented within a child node of its own named 'memories' without
+any compatible. The Real Time Media Independent Interface controllers
+(MII_RT and MII_G_RT), and the CFG sub-module are represented as syscon
+nodes. The ICSSG CFG module has clock muxes for IEP clock and CORE clock,
+these clk nodes are added under the CFG child node 'clocks'. The default
+parents for these mux clocks are also assigned.
+
+The DT nodes use all standard properties. The regs property in the
+PRU/RTU/Tx_PRU nodes define the addresses for the Instruction RAM, the
+Debug and Control sub-modules for that PRU core. The firmware for each
+PRU/RTU/Tx_PRU core is defined through a 'firmware-name' property.
+
+The default names for the firmware images for each PRU, RTU and Tx_PRU
+cores are defined as follows (these can be adjusted either in derivative
+board dts files or through sysfs at runtime if required):
+ ICSSG0 PRU0 Core    : am65x-pru0_0-fw   ; PRU1 Core    : am65x-pru0_1-fw
+ ICSSG0 RTU0 Core    : am65x-rtu0_0-fw   ; RTU1 Core    : am65x-rtu0_1-fw
+ ICSSG0 Tx_PRU0 Core : am65x-txpru0_0-fw ; Tx_PRU1 Core : am65x-txpru0_1-fw
+ ICSSG1 PRU0 Core    : am65x-pru1_0-fw   ; PRU1 Core    : am65x-pru1_1-fw
+ ICSSG1 RTU0 Core    : am65x-rtu1_0-fw   ; RTU1 Core    : am65x-rtu1_1-fw
+ ICSSG1 Tx_PRU0 Core : am65x-txpru1_0-fw ; Tx_PRU1 Core : am65x-txpru1_1-fw
+ ICSSG2 PRU0 Core    : am65x-pru2_0-fw   ; PRU1 Core    : am65x-pru2_1-fw
+ ICSSG2 RTU0 Core    : am65x-rtu2_0-fw   ; RTU1 Core    : am65x-rtu2_1-fw
+ ICSSG2 Tx_PRU0 Core : am65x-txpru2_0-fw ; Tx_PRU1 Core : am65x-txpru2_1-fw
+
+Note:
+1. The ICSSG nodes are all added as per the SR2.0 device. Any sub-module IP
+   differences need to be handled within the driver using SoC device match
+   logic or separate dts/overlay files (if needs to be supported) with the
+   Tx_PRU nodes expected to be disabled at the minimum.
+2. The ICSSG INTC on AM65x SoCs share 5, 6, 7 host interrupts with other
+   processors, so use the 'ti,irqs-reserved' property in derivative board
+   dts files _if_ any of them should not be handled by the host OS.
+3. There are few more sub-modules like the Industrial Ethernet Peripherals
+   (IEPs), MDIO, PWM, UART that do not have bindings and so will be added
+   in the future.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
+Link: https://lore.kernel.org/r/20210304160712.8452-2-s-anna@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 393 +++++++++++++++++++++++
+ 1 file changed, 393 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index 3c36ae6d7816..6d2662588565 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -923,4 +923,397 @@ ehrpwm5: pwm@3050000 {
+ 		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
+ 		clock-names = "tbclk", "fck";
+ 	};
++
++	icssg0: icssg@b000000 {
++		compatible = "ti,am654-icssg";
++		reg = <0x00 0xb000000 0x00 0x80000>;
++		power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <0x0 0x00 0xb000000 0x80000>;
++
++		icssg0_mem: memories@0 {
++			reg = <0x0 0x2000>,
++			      <0x2000 0x2000>,
++			      <0x10000 0x10000>;
++			reg-names = "dram0", "dram1",
++				    "shrdram2";
++		};
++
++		icssg0_cfg: cfg@26000 {
++			compatible = "ti,pruss-cfg", "syscon";
++			reg = <0x26000 0x200>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x26000 0x2000>;
++
++			clocks {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				icssg0_coreclk_mux: coreclk-mux@3c {
++					reg = <0x3c>;
++					#clock-cells = <0>;
++					clocks = <&k3_clks 62 19>, /* icssg0_core_clk */
++						 <&k3_clks 62 3>;  /* icssg0_iclk */
++					assigned-clocks = <&icssg0_coreclk_mux>;
++					assigned-clock-parents = <&k3_clks 62 3>;
++				};
++
++				icssg0_iepclk_mux: iepclk-mux@30 {
++					reg = <0x30>;
++					#clock-cells = <0>;
++					clocks = <&k3_clks 62 10>,	/* icssg0_iep_clk */
++						 <&icssg0_coreclk_mux>;	/* core_clk */
++					assigned-clocks = <&icssg0_iepclk_mux>;
++					assigned-clock-parents = <&icssg0_coreclk_mux>;
++				};
++			};
++		};
++
++		icssg0_mii_rt: mii-rt@32000 {
++			compatible = "ti,pruss-mii", "syscon";
++			reg = <0x32000 0x100>;
++		};
++
++		icssg0_mii_g_rt: mii-g-rt@33000 {
++			compatible = "ti,pruss-mii-g", "syscon";
++			reg = <0x33000 0x1000>;
++		};
++
++		icssg0_intc: interrupt-controller@20000 {
++			compatible = "ti,icssg-intc";
++			reg = <0x20000 0x2000>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "host_intr0", "host_intr1",
++					  "host_intr2", "host_intr3",
++					  "host_intr4", "host_intr5",
++					  "host_intr6", "host_intr7";
++		};
++
++		pru0_0: pru@34000 {
++			compatible = "ti,am654-pru";
++			reg = <0x34000 0x4000>,
++			      <0x22000 0x100>,
++			      <0x22400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-pru0_0-fw";
++		};
++
++		rtu0_0: rtu@4000 {
++			compatible = "ti,am654-rtu";
++			reg = <0x4000 0x2000>,
++			      <0x23000 0x100>,
++			      <0x23400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-rtu0_0-fw";
++		};
++
++		tx_pru0_0: txpru@a000 {
++			compatible = "ti,am654-tx-pru";
++			reg = <0xa000 0x1800>,
++			      <0x25000 0x100>,
++			      <0x25400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-txpru0_0-fw";
++		};
++
++		pru0_1: pru@38000 {
++			compatible = "ti,am654-pru";
++			reg = <0x38000 0x4000>,
++			      <0x24000 0x100>,
++			      <0x24400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-pru0_1-fw";
++		};
++
++		rtu0_1: rtu@6000 {
++			compatible = "ti,am654-rtu";
++			reg = <0x6000 0x2000>,
++			      <0x23800 0x100>,
++			      <0x23c00 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-rtu0_1-fw";
++		};
++
++		tx_pru0_1: txpru@c000 {
++			compatible = "ti,am654-tx-pru";
++			reg = <0xc000 0x1800>,
++			      <0x25800 0x100>,
++			      <0x25c00 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-txpru0_1-fw";
++		};
++	};
++
++	icssg1: icssg@b100000 {
++		compatible = "ti,am654-icssg";
++		reg = <0x00 0xb100000 0x00 0x80000>;
++		power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <0x0 0x00 0xb100000 0x80000>;
++
++		icssg1_mem: memories@0 {
++			reg = <0x0 0x2000>,
++			      <0x2000 0x2000>,
++			      <0x10000 0x10000>;
++			reg-names = "dram0", "dram1",
++				    "shrdram2";
++		};
++
++		icssg1_cfg: cfg@26000 {
++			compatible = "ti,pruss-cfg", "syscon";
++			reg = <0x26000 0x200>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x26000 0x2000>;
++
++			clocks {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				icssg1_coreclk_mux: coreclk-mux@3c {
++					reg = <0x3c>;
++					#clock-cells = <0>;
++					clocks = <&k3_clks 63 19>, /* icssg1_core_clk */
++						 <&k3_clks 63 3>;  /* icssg1_iclk */
++					assigned-clocks = <&icssg1_coreclk_mux>;
++					assigned-clock-parents = <&k3_clks 63 3>;
++				};
++
++				icssg1_iepclk_mux: iepclk-mux@30 {
++					reg = <0x30>;
++					#clock-cells = <0>;
++					clocks = <&k3_clks 63 10>,	/* icssg1_iep_clk */
++						 <&icssg1_coreclk_mux>;	/* core_clk */
++					assigned-clocks = <&icssg1_iepclk_mux>;
++					assigned-clock-parents = <&icssg1_coreclk_mux>;
++				};
++			};
++		};
++
++		icssg1_mii_rt: mii-rt@32000 {
++			compatible = "ti,pruss-mii", "syscon";
++			reg = <0x32000 0x100>;
++		};
++
++		icssg1_mii_g_rt: mii-g-rt@33000 {
++			compatible = "ti,pruss-mii-g", "syscon";
++			reg = <0x33000 0x1000>;
++		};
++
++		icssg1_intc: interrupt-controller@20000 {
++			compatible = "ti,icssg-intc";
++			reg = <0x20000 0x2000>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "host_intr0", "host_intr1",
++					  "host_intr2", "host_intr3",
++					  "host_intr4", "host_intr5",
++					  "host_intr6", "host_intr7";
++		};
++
++		pru1_0: pru@34000 {
++			compatible = "ti,am654-pru";
++			reg = <0x34000 0x4000>,
++			      <0x22000 0x100>,
++			      <0x22400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-pru1_0-fw";
++		};
++
++		rtu1_0: rtu@4000 {
++			compatible = "ti,am654-rtu";
++			reg = <0x4000 0x2000>,
++			      <0x23000 0x100>,
++			      <0x23400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-rtu1_0-fw";
++		};
++
++		tx_pru1_0: txpru@a000 {
++			compatible = "ti,am654-tx-pru";
++			reg = <0xa000 0x1800>,
++			      <0x25000 0x100>,
++			      <0x25400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-txpru1_0-fw";
++		};
++
++		pru1_1: pru@38000 {
++			compatible = "ti,am654-pru";
++			reg = <0x38000 0x4000>,
++			      <0x24000 0x100>,
++			      <0x24400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-pru1_1-fw";
++		};
++
++		rtu1_1: rtu@6000 {
++			compatible = "ti,am654-rtu";
++			reg = <0x6000 0x2000>,
++			      <0x23800 0x100>,
++			      <0x23c00 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-rtu1_1-fw";
++		};
++
++		tx_pru1_1: txpru@c000 {
++			compatible = "ti,am654-tx-pru";
++			reg = <0xc000 0x1800>,
++			      <0x25800 0x100>,
++			      <0x25c00 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-txpru1_1-fw";
++		};
++	};
++
++	icssg2: icssg@b200000 {
++		compatible = "ti,am654-icssg";
++		reg = <0x00 0xb200000 0x00 0x80000>;
++		power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges = <0x0 0x00 0xb200000 0x80000>;
++
++		icssg2_mem: memories@0 {
++			reg = <0x0 0x2000>,
++			      <0x2000 0x2000>,
++			      <0x10000 0x10000>;
++			reg-names = "dram0", "dram1",
++				    "shrdram2";
++		};
++
++		icssg2_cfg: cfg@26000 {
++			compatible = "ti,pruss-cfg", "syscon";
++			reg = <0x26000 0x200>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0x0 0x26000 0x2000>;
++
++			clocks {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				icssg2_coreclk_mux: coreclk-mux@3c {
++					reg = <0x3c>;
++					#clock-cells = <0>;
++					clocks = <&k3_clks 64 19>, /* icssg1_core_clk */
++						 <&k3_clks 64 3>;  /* icssg1_iclk */
++					assigned-clocks = <&icssg2_coreclk_mux>;
++					assigned-clock-parents = <&k3_clks 64 3>;
++				};
++
++				icssg2_iepclk_mux: iepclk-mux@30 {
++					reg = <0x30>;
++					#clock-cells = <0>;
++					clocks = <&k3_clks 64 10>,	/* icssg1_iep_clk */
++						 <&icssg2_coreclk_mux>;	/* core_clk */
++					assigned-clocks = <&icssg2_iepclk_mux>;
++					assigned-clock-parents = <&icssg2_coreclk_mux>;
++				};
++			};
++		};
++
++		icssg2_mii_rt: mii-rt@32000 {
++			compatible = "ti,pruss-mii", "syscon";
++			reg = <0x32000 0x100>;
++		};
++
++		icssg2_mii_g_rt: mii-g-rt@33000 {
++			compatible = "ti,pruss-mii-g", "syscon";
++			reg = <0x33000 0x1000>;
++		};
++
++		icssg2_intc: interrupt-controller@20000 {
++			compatible = "ti,icssg-intc";
++			reg = <0x20000 0x2000>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++			interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "host_intr0", "host_intr1",
++					  "host_intr2", "host_intr3",
++					  "host_intr4", "host_intr5",
++					  "host_intr6", "host_intr7";
++		};
++
++		pru2_0: pru@34000 {
++			compatible = "ti,am654-pru";
++			reg = <0x34000 0x4000>,
++			      <0x22000 0x100>,
++			      <0x22400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-pru2_0-fw";
++		};
++
++		rtu2_0: rtu@4000 {
++			compatible = "ti,am654-rtu";
++			reg = <0x4000 0x2000>,
++			      <0x23000 0x100>,
++			      <0x23400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-rtu2_0-fw";
++		};
++
++		tx_pru2_0: txpru@a000 {
++			compatible = "ti,am654-tx-pru";
++			reg = <0xa000 0x1800>,
++			      <0x25000 0x100>,
++			      <0x25400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-txpru2_0-fw";
++		};
++
++		pru2_1: pru@38000 {
++			compatible = "ti,am654-pru";
++			reg = <0x38000 0x4000>,
++			      <0x24000 0x100>,
++			      <0x24400 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-pru2_1-fw";
++		};
++
++		rtu2_1: rtu@6000 {
++			compatible = "ti,am654-rtu";
++			reg = <0x6000 0x2000>,
++			      <0x23800 0x100>,
++			      <0x23c00 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-rtu2_1-fw";
++		};
++
++		tx_pru2_1: txpru@c000 {
++			compatible = "ti,am654-tx-pru";
++			reg = <0xc000 0x1800>,
++			      <0x25800 0x100>,
++			      <0x25c00 0x100>;
++			reg-names = "iram", "control", "debug";
++			firmware-name = "am65x-txpru2_1-fw";
++		};
++	};
+ };

board/PSG/iot2050/files/patches-5.10/0009-arm64-dts-ti-k3-am65-mcu-Add-RTI-watchdog-entry.patch

@@ -0,0 +1,38 @@
+From 71ddd11e950e1b60a750cdf75c2c21148e7c9a8f Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Sat, 20 Feb 2021 13:49:51 +0100
+Subject: [PATCH] arm64: dts: ti: k3-am65-mcu: Add RTI watchdog entry
+
+Add the DT entry for a watchdog based on RTI1.
+
+On SR1.0 silicon, it requires additional firmware on the MCU R5F cores
+to handle the expiry, e.g. https://github.com/siemens/k3-rti-wdt. As
+this firmware will also lock the power domain to protect it against
+premature shutdown, mark it shared.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Acked-by: Praneeth Bajjuri <praneeth@ti.com>
+Link: https://lore.kernel.org/r/279c20fa-6e5e-4f88-9cd1-f76297a28a19@web.de
+---
+ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+index 7454c8cec0cc..0388c02c2203 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+@@ -308,4 +308,13 @@ mcu_r5fss0_core1: r5f@41400000 {
+ 			ti,loczrama = <1>;
+ 		};
+ 	};
++
++	mcu_rti1: watchdog@40610000 {
++		compatible = "ti,j7-rti-wdt";
++		reg = <0x0 0x40610000 0x0 0x100>;
++		clocks = <&k3_clks 135 0>;
++		power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>;
++		assigned-clocks = <&k3_clks 135 0>;
++		assigned-clock-parents = <&k3_clks 135 4>;
++	};
+ };

board/PSG/iot2050/files/patches-5.10/0010-arm64-dts-ti-Add-support-for-Siemens-IOT2050-boards.patch

@@ -0,0 +1,836 @@
+From 4fed948c09670556245e80c9f729a7d651fc4900 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Thu, 11 Mar 2021 15:33:43 +0100
+Subject: [PATCH] arm64: dts: ti: Add support for Siemens IOT2050 boards
+
+Add support for two Siemens SIMATIC IOT2050 variants, Basic and
+Advanced. They are based on the TI AM6528 GP and AM6548 SOCs HS, thus
+differ in their number of cores and availability of security features.
+Furthermore the Advanced version comes with more RAM, an eMMC and a few
+internal differences.
+
+Based on original version by Le Jin.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
+Link: https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+Link: https://github.com/siemens/meta-iot2050
+Link: https://lore.kernel.org/r/4fb05969102d14d230e03ca4312ef9706efa61e6.1615473223.git.jan.kiszka@siemens.com
+---
+ arch/arm64/boot/dts/ti/Makefile               |   2 +
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 655 ++++++++++++++++++
+ .../boot/dts/ti/k3-am6528-iot2050-basic.dts   |  61 ++
+ .../dts/ti/k3-am6548-iot2050-advanced.dts     |  60 ++
+ 4 files changed, 778 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
+
+diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
+index 65506f21ba30..22108491f16e 100644
+--- a/arch/arm64/boot/dts/ti/Makefile
++++ b/arch/arm64/boot/dts/ti/Makefile
+@@ -7,6 +7,8 @@
+ #
+ 
+ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
++dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
++dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
+ 
+ dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+ 
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+new file mode 100644
+index 000000000000..de763ca9251c
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -0,0 +1,655 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2018-2021
++ *
++ * Authors:
++ *   Le Jin <le.jin@siemens.com>
++ *   Jan Kiszka <jan.kiszk@siemens.com>
++ *
++ * Common bits of the IOT2050 Basic and Advanced variants
++ */
++
++/dts-v1/;
++
++#include "k3-am654.dtsi"
++#include <dt-bindings/phy/phy.h>
++
++/ {
++	aliases {
++		spi0 = &mcu_spi0;
++	};
++
++	chosen {
++		stdout-path = "serial3:115200n8";
++		bootargs = "earlycon=ns16550a,mmio32,0x02810000";
++	};
++
++	reserved-memory {
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++
++		secure_ddr: secure-ddr@9e800000 {
++			reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */
++			alignment = <0x1000>;
++			no-map;
++		};
++
++		mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
++			compatible = "shared-dma-pool";
++			reg = <0 0xa0000000 0 0x100000>;
++			no-map;
++		};
++
++		mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
++			compatible = "shared-dma-pool";
++			reg = <0 0xa0100000 0 0xf00000>;
++			no-map;
++		};
++
++		mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
++			compatible = "shared-dma-pool";
++			reg = <0 0xa1000000 0 0x100000>;
++			no-map;
++		};
++
++		mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
++			compatible = "shared-dma-pool";
++			reg = <0 0xa1100000 0 0xf00000>;
++			no-map;
++		};
++
++		rtos_ipc_memory_region: ipc-memories@a2000000 {
++			reg = <0x00 0xa2000000 0x00 0x00200000>;
++			alignment = <0x1000>;
++			no-map;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&leds_pins_default>;
++
++		status-led-red {
++			gpios = <&wkup_gpio0 32 GPIO_ACTIVE_HIGH>;
++			panic-indicator;
++		};
++
++		status-led-green {
++			gpios = <&wkup_gpio0 24 GPIO_ACTIVE_HIGH>;
++		};
++
++		user-led1-red {
++			gpios = <&pcal9535_3 14 GPIO_ACTIVE_HIGH>;
++		};
++
++		user-led1-green {
++			gpios = <&pcal9535_2 15 GPIO_ACTIVE_HIGH>;
++		};
++
++		user-led2-red {
++			gpios = <&wkup_gpio0 17 GPIO_ACTIVE_HIGH>;
++		};
++
++		user-led2-green {
++			gpios = <&wkup_gpio0 22 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	dp_refclk: clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <19200000>;
++	};
++};
++
++&wkup_pmx0 {
++	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
++		pinctrl-single,pins = <
++			/* (AC7) WKUP_I2C0_SCL */
++			AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT,  0)
++			/* (AD6) WKUP_I2C0_SDA */
++			AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT,  0)
++		>;
++	};
++
++	mcu_i2c0_pins_default: mcu-i2c0-pins-default {
++		pinctrl-single,pins = <
++			/* (AD8) MCU_I2C0_SCL */
++			AM65X_WKUP_IOPAD(0x00e8, PIN_INPUT,  0)
++			/* (AD7) MCU_I2C0_SDA */
++			AM65X_WKUP_IOPAD(0x00ec, PIN_INPUT,  0)
++		>;
++	};
++
++	arduino_i2c_aio_switch_pins_default: arduino-i2c-aio-switch-pins-default {
++		pinctrl-single,pins = <
++			/* (R2) WKUP_GPIO0_21 */
++			AM65X_WKUP_IOPAD(0x0024, PIN_OUTPUT, 7)
++		>;
++	};
++
++	push_button_pins_default: push-button-pins-default {
++		pinctrl-single,pins = <
++			/* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */
++			AM65X_WKUP_IOPAD(0x0034, PIN_INPUT,  7)
++		>;
++	};
++
++	arduino_uart_pins_default: arduino-uart-pins-default {
++		pinctrl-single,pins = <
++			/* (P4) MCU_UART0_RXD */
++			AM65X_WKUP_IOPAD(0x0044, PIN_INPUT,  4)
++			/* (P5) MCU_UART0_TXD */
++			AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4)
++		>;
++	};
++
++	arduino_io_d2_to_d3_pins_default: arduino-io-d2-to-d3-pins-default {
++		pinctrl-single,pins = <
++			/* (P1) WKUP_GPIO0_31 */
++			AM65X_WKUP_IOPAD(0x004C, PIN_OUTPUT, 7)
++			/* (N3) WKUP_GPIO0_33 */
++			AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 7)
++		>;
++	};
++
++	arduino_io_oe_pins_default: arduino-io-oe-pins-default {
++		pinctrl-single,pins = <
++			/* (N4) WKUP_GPIO0_34 */
++			AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 7)
++			/* (M2) WKUP_GPIO0_36 */
++			AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 7)
++			/* (M3) WKUP_GPIO0_37 */
++			AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 7)
++			/* (M4) WKUP_GPIO0_38 */
++			AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 7)
++			/* (M1) WKUP_GPIO0_41 */
++			AM65X_WKUP_IOPAD(0x0074, PIN_OUTPUT, 7)
++		>;
++	};
++
++	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
++		pinctrl-single,pins = <
++			/* (V1) MCU_OSPI0_CLK */
++			AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0)
++			/* (U2) MCU_OSPI0_DQS */
++			AM65X_WKUP_IOPAD(0x0008, PIN_INPUT,  0)
++			/* (U4) MCU_OSPI0_D0 */
++			AM65X_WKUP_IOPAD(0x000c, PIN_INPUT,  0)
++			/* (U5) MCU_OSPI0_D1 */
++			AM65X_WKUP_IOPAD(0x0010, PIN_INPUT,  0)
++			/* (R4) MCU_OSPI0_CSn0 */
++			AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0)
++		>;
++	};
++
++	db9_com_mode_pins_default: db9-com-mode-pins-default {
++		pinctrl-single,pins = <
++			/* (AD3) WKUP_GPIO0_5, used as uart0 mode 0 */
++			AM65X_WKUP_IOPAD(0x00c4, PIN_OUTPUT, 7)
++			/* (AC3) WKUP_GPIO0_4, used as uart0 mode 1 */
++			AM65X_WKUP_IOPAD(0x00c0, PIN_OUTPUT, 7)
++			/* (AC1) WKUP_GPIO0_7, used as uart0 term */
++			AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 7)
++			/* (AC2) WKUP_GPIO0_6, used as uart0 en */
++			AM65X_WKUP_IOPAD(0x00c8, PIN_OUTPUT, 7)
++		>;
++	};
++
++	leds_pins_default: leds-pins-default {
++		pinctrl-single,pins = <
++			/* (T2) WKUP_GPIO0_17, used as user led1 red */
++			AM65X_WKUP_IOPAD(0x0014, PIN_OUTPUT, 7)
++			/* (R3) WKUP_GPIO0_22, used as user led1 green */
++			AM65X_WKUP_IOPAD(0x0028, PIN_OUTPUT, 7)
++			/* (R5) WKUP_GPIO0_24, used as status led red */
++			AM65X_WKUP_IOPAD(0x0030, PIN_OUTPUT, 7)
++			/* (N2) WKUP_GPIO0_32, used as status led green */
++			AM65X_WKUP_IOPAD(0x0050, PIN_OUTPUT, 7)
++		>;
++	};
++
++	mcu_spi0_pins_default: mcu-spi0-pins-default {
++		pinctrl-single,pins = <
++			/* (Y1) MCU_SPI0_CLK */
++			AM65X_WKUP_IOPAD(0x0090, PIN_INPUT,  0)
++			/* (Y3) MCU_SPI0_D0 */
++			AM65X_WKUP_IOPAD(0x0094, PIN_INPUT,  0)
++			/* (Y2) MCU_SPI0_D1 */
++			AM65X_WKUP_IOPAD(0x0098, PIN_INPUT,  0)
++			/* (Y4) MCU_SPI0_CS0 */
++			AM65X_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0)
++		>;
++	};
++
++	minipcie_pins_default: minipcie-pins-default {
++		pinctrl-single,pins = <
++			/* (P2) MCU_OSPI1_DQS.WKUP_GPIO0_27 */
++			AM65X_WKUP_IOPAD(0x003C, PIN_OUTPUT, 7)
++		>;
++	};
++};
++
++&main_pmx0 {
++	main_uart1_pins_default: main-uart1-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0174, PIN_INPUT,  6)  /* (AE23) UART1_RXD */
++			AM65X_IOPAD(0x014c, PIN_OUTPUT, 6)  /* (AD23) UART1_TXD */
++			AM65X_IOPAD(0x0178, PIN_INPUT,  6)  /* (AD22) UART1_CTSn */
++			AM65X_IOPAD(0x017c, PIN_OUTPUT, 6)  /* (AC21) UART1_RTSn */
++		>;
++	};
++
++	main_i2c3_pins_default: main-i2c3-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x01c0, PIN_INPUT,  2)  /* (AF13) I2C3_SCL */
++			AM65X_IOPAD(0x01d4, PIN_INPUT,  2)  /* (AG12) I2C3_SDA */
++		>;
++	};
++
++	main_mmc1_pins_default: main-mmc1-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0)  /* (C27) MMC1_CLK */
++			AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP,   0)  /* (C28) MMC1_CMD */
++			AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP,   0)  /* (D28) MMC1_DAT0 */
++			AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP,   0)  /* (E27) MMC1_DAT1 */
++			AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP,   0)  /* (D26) MMC1_DAT2 */
++			AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP,   0)  /* (D27) MMC1_DAT3 */
++			AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP,   0)  /* (B24) MMC1_SDCD */
++			AM65X_IOPAD(0x02e0, PIN_INPUT_PULLUP,   0)  /* (C24) MMC1_SDWP */
++		>;
++	};
++
++	usb0_pins_default: usb0-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0)  /* (AD9) USB0_DRVVBUS */
++		>;
++	};
++
++	usb1_pins_default: usb1-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0)  /* (AC8) USB1_DRVVBUS */
++		>;
++	};
++
++	arduino_io_d4_to_d9_pins_default: arduino-io-d4-to-d9-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0084, PIN_OUTPUT, 7)  /* (AG18) GPIO0_33 */
++			AM65X_IOPAD(0x008C, PIN_OUTPUT, 7)  /* (AF17) GPIO0_35 */
++			AM65X_IOPAD(0x0098, PIN_OUTPUT, 7)  /* (AH16) GPIO0_38 */
++			AM65X_IOPAD(0x00AC, PIN_OUTPUT, 7)  /* (AH15) GPIO0_43 */
++			AM65X_IOPAD(0x00C0, PIN_OUTPUT, 7)  /* (AG15) GPIO0_48 */
++			AM65X_IOPAD(0x00CC, PIN_OUTPUT, 7)  /* (AD15) GPIO0_51 */
++		>;
++	};
++
++	dss_vout1_pins_default: dss-vout1-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0000, PIN_OUTPUT, 1)  /* VOUT1_DATA0 */
++			AM65X_IOPAD(0x0004, PIN_OUTPUT, 1)  /* VOUT1_DATA1 */
++			AM65X_IOPAD(0x0008, PIN_OUTPUT, 1)  /* VOUT1_DATA2 */
++			AM65X_IOPAD(0x000c, PIN_OUTPUT, 1)  /* VOUT1_DATA3 */
++			AM65X_IOPAD(0x0010, PIN_OUTPUT, 1)  /* VOUT1_DATA4 */
++			AM65X_IOPAD(0x0014, PIN_OUTPUT, 1)  /* VOUT1_DATA5 */
++			AM65X_IOPAD(0x0018, PIN_OUTPUT, 1)  /* VOUT1_DATA6 */
++			AM65X_IOPAD(0x001c, PIN_OUTPUT, 1)  /* VOUT1_DATA7 */
++			AM65X_IOPAD(0x0020, PIN_OUTPUT, 1)  /* VOUT1_DATA8 */
++			AM65X_IOPAD(0x0024, PIN_OUTPUT, 1)  /* VOUT1_DATA9 */
++			AM65X_IOPAD(0x0028, PIN_OUTPUT, 1)  /* VOUT1_DATA10 */
++			AM65X_IOPAD(0x002c, PIN_OUTPUT, 1)  /* VOUT1_DATA11 */
++			AM65X_IOPAD(0x0030, PIN_OUTPUT, 1)  /* VOUT1_DATA12 */
++			AM65X_IOPAD(0x0034, PIN_OUTPUT, 1)  /* VOUT1_DATA13 */
++			AM65X_IOPAD(0x0038, PIN_OUTPUT, 1)  /* VOUT1_DATA14 */
++			AM65X_IOPAD(0x003c, PIN_OUTPUT, 1)  /* VOUT1_DATA15 */
++			AM65X_IOPAD(0x0040, PIN_OUTPUT, 1)  /* VOUT1_DATA16 */
++			AM65X_IOPAD(0x0044, PIN_OUTPUT, 1)  /* VOUT1_DATA17 */
++			AM65X_IOPAD(0x0048, PIN_OUTPUT, 1)  /* VOUT1_DATA18 */
++			AM65X_IOPAD(0x004c, PIN_OUTPUT, 1)  /* VOUT1_DATA19 */
++			AM65X_IOPAD(0x0050, PIN_OUTPUT, 1)  /* VOUT1_DATA20 */
++			AM65X_IOPAD(0x0054, PIN_OUTPUT, 1)  /* VOUT1_DATA21 */
++			AM65X_IOPAD(0x0058, PIN_OUTPUT, 1)  /* VOUT1_DATA22 */
++			AM65X_IOPAD(0x005c, PIN_OUTPUT, 1)  /* VOUT1_DATA23 */
++			AM65X_IOPAD(0x0060, PIN_OUTPUT, 1)  /* VOUT1_VSYNC */
++			AM65X_IOPAD(0x0064, PIN_OUTPUT, 1)  /* VOUT1_HSYNC */
++			AM65X_IOPAD(0x0068, PIN_OUTPUT, 1)  /* VOUT1_PCLK */
++			AM65X_IOPAD(0x006c, PIN_OUTPUT, 1)  /* VOUT1_DE */
++		>;
++	};
++
++	dp_pins_default: dp-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0078, PIN_OUTPUT, 7)  /* (AF18) DP rst_n */
++		>;
++	};
++
++	main_i2c2_pins_default: main-i2c2-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0074, PIN_INPUT,  5)  /* (T27) I2C2_SCL */
++			AM65X_IOPAD(0x0070, PIN_INPUT,  5)  /* (R25) I2C2_SDA */
++		>;
++	};
++};
++
++&main_pmx1 {
++	main_i2c0_pins_default: main-i2c0-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0000, PIN_INPUT,  0)  /* (D20) I2C0_SCL */
++			AM65X_IOPAD(0x0004, PIN_INPUT,  0)  /* (C21) I2C0_SDA */
++		>;
++	};
++
++	main_i2c1_pins_default: main-i2c1-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0008, PIN_INPUT,  0)  /* (B21) I2C1_SCL */
++			AM65X_IOPAD(0x000c, PIN_INPUT,  0)  /* (E21) I2C1_SDA */
++		>;
++	};
++
++	ecap0_pins_default: ecap0-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x0010, PIN_INPUT,  0)  /* (D21) ECAP0_IN_APWM_OUT */
++		>;
++	};
++};
++
++&wkup_uart0 {
++	/* Wakeup UART is used by System firmware */
++	status = "reserved";
++};
++
++&main_uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_uart1_pins_default>;
++};
++
++&main_uart2 {
++	status = "disabled";
++};
++
++&mcu_uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&arduino_uart_pins_default>;
++};
++
++&main_gpio0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&arduino_io_d4_to_d9_pins_default>;
++	gpio-line-names =
++		"main_gpio0-base", "", "", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "", "", "",
++		"", "", "", "IO4", "", "IO5", "", "", "IO6", "",
++		"", "", "", "IO7", "", "", "", "", "IO8", "",
++		"", "IO9";
++};
++
++&wkup_gpio0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <
++		&arduino_io_d2_to_d3_pins_default
++		&arduino_i2c_aio_switch_pins_default
++		&arduino_io_oe_pins_default
++		&push_button_pins_default
++		&db9_com_mode_pins_default
++	>;
++	gpio-line-names =
++		/* 0..9 */
++		"wkup_gpio0-base", "", "", "", "UART0-mode1", "UART0-mode0",
++		"UART0-enable", "UART0-terminate", "", "WIFI-disable",
++		/* 10..19 */
++		"", "", "", "", "", "", "", "", "", "",
++		/* 20..29 */
++		"", "A4A5-I2C-mux", "", "", "", "USER-button", "", "", "","IO0",
++		/* 30..39 */
++		"IO1", "IO2", "", "IO3", "IO17-direction", "A5",
++		"IO16-direction", "IO15-direction", "IO14-direction", "A3",
++		/* 40..49 */
++		"", "IO18-direction", "A4", "A2", "A1", "A0", "", "", "IO13",
++		"IO11",
++		/* 50..51 */
++		"IO12", "IO10";
++};
++
++&wkup_i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&wkup_i2c0_pins_default>;
++	clock-frequency = <400000>;
++};
++
++&mcu_i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mcu_i2c0_pins_default>;
++	clock-frequency = <400000>;
++
++	psu: regulator@60 {
++		compatible = "ti,tps62363";
++		reg =  <0x60>;
++		regulator-name = "tps62363-vout";
++		regulator-min-microvolt = <500000>;
++		regulator-max-microvolt = <1500000>;
++		regulator-boot-on;
++		ti,vsel0-state-high;
++		ti,vsel1-state-high;
++		ti,enable-vout-discharge;
++	};
++
++	/* D4200 */
++	pcal9535_1: gpio@20 {
++		compatible = "nxp,pcal9535";
++		reg = <0x20>;
++		#gpio-cells = <2>;
++		gpio-controller;
++		gpio-line-names =
++			"A0-pull", "A1-pull", "A2-pull", "A3-pull", "A4-pull",
++			"A5-pull", "", "",
++			"IO14-enable", "IO15-enable", "IO16-enable",
++			"IO17-enable", "IO18-enable", "IO19-enable";
++	};
++
++	/* D4201 */
++	pcal9535_2: gpio@21 {
++		compatible = "nxp,pcal9535";
++		reg = <0x21>;
++		#gpio-cells = <2>;
++		gpio-controller;
++		gpio-line-names =
++			"IO0-direction", "IO1-direction", "IO2-direction",
++			"IO3-direction", "IO4-direction", "IO5-direction",
++			"IO6-direction", "IO7-direction",
++			"IO8-direction", "IO9-direction", "IO10-direction",
++			"IO11-direction", "IO12-direction", "IO13-direction",
++			"IO19-direction";
++	};
++
++	/* D4202 */
++	pcal9535_3: gpio@25 {
++		compatible = "nxp,pcal9535";
++		reg = <0x25>;
++		#gpio-cells = <2>;
++		gpio-controller;
++		gpio-line-names =
++			"IO0-pull", "IO1-pull", "IO2-pull", "IO3-pull",
++			"IO4-pull", "IO5-pull", "IO6-pull", "IO7-pull",
++			"IO8-pull", "IO9-pull", "IO10-pull", "IO11-pull",
++			"IO12-pull", "IO13-pull";
++	};
++};
++
++&main_i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_i2c0_pins_default>;
++	clock-frequency = <400000>;
++
++	rtc: rtc8564@51 {
++		compatible = "nxp,pcf8563";
++		reg = <0x51>;
++	};
++
++	eeprom: eeprom@54 {
++		compatible = "atmel,24c08";
++		reg = <0x54>;
++		pagesize = <16>;
++	};
++};
++
++&main_i2c1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_i2c1_pins_default>;
++	clock-frequency = <400000>;
++};
++
++&main_i2c2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_i2c2_pins_default>;
++	clock-frequency = <400000>;
++};
++
++&main_i2c3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_i2c3_pins_default>;
++	clock-frequency = <400000>;
++
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	edp-bridge@f {
++		compatible = "toshiba,tc358767";
++		reg = <0x0f>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&dp_pins_default>;
++		reset-gpios = <&main_gpio0 30 GPIO_ACTIVE_HIGH>;
++
++		clock-names = "ref";
++		clocks = <&dp_refclk>;
++
++		toshiba,hpd-pin = <0>;
++
++		ports {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			port@1 {
++				reg = <1>;
++
++				bridge_in: endpoint {
++					remote-endpoint = <&dpi_out>;
++				};
++			};
++		};
++	};
++};
++
++&mcu_cpsw {
++	status = "disabled";
++};
++
++&ecap0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ecap0_pins_default>;
++};
++
++&sdhci1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_mmc1_pins_default>;
++	ti,driver-strength-ohm = <50>;
++	disable-wp;
++};
++
++&usb0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&usb0_pins_default>;
++	dr_mode = "host";
++};
++
++&usb1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&usb1_pins_default>;
++	dr_mode = "host";
++};
++
++&mcu_spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mcu_spi0_pins_default>;
++
++	#address-cells = <1>;
++	#size-cells= <0>;
++	ti,pindir-d0-out-d1-in = <1>;
++};
++
++&tscadc0 {
++	status = "disabled";
++};
++
++&tscadc1 {
++	adc {
++		ti,adc-channels = <0 1 2 3 4 5>;
++	};
++};
++
++&ospi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0x0>;
++		spi-tx-bus-width = <1>;
++		spi-rx-bus-width = <1>;
++		spi-max-frequency = <50000000>;
++		cdns,tshsl-ns = <60>;
++		cdns,tsd2d-ns = <60>;
++		cdns,tchsh-ns = <60>;
++		cdns,tslch-ns = <60>;
++		cdns,read-delay = <2>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++	};
++};
++
++&dss {
++	pinctrl-names = "default";
++	pinctrl-0 = <&dss_vout1_pins_default>;
++
++	assigned-clocks = <&k3_clks 67 2>;
++	assigned-clock-parents = <&k3_clks 67 5>;
++};
++
++&dss_ports {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	port@1 {
++		reg = <1>;
++
++		dpi_out: endpoint {
++			remote-endpoint = <&bridge_in>;
++		};
++	};
++};
++
++&serdes0 {
++	status = "disabled";
++};
++
++&pcie0_rc {
++	status = "disabled";
++};
++
++&pcie0_ep {
++	status = "disabled";
++};
++
++&pcie1_rc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&minipcie_pins_default>;
++
++	num-lanes = <1>;
++	phys = <&serdes1 PHY_TYPE_PCIE 0>;
++	phy-names = "pcie-phy0";
++	reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
++};
++
++&pcie1_ep {
++	status = "disabled";
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+new file mode 100644
+index 000000000000..4f7e3f2a6265
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+@@ -0,0 +1,61 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2018-2021
++ *
++ * Authors:
++ *   Le Jin <le.jin@siemens.com>
++ *   Jan Kiszka <jan.kiszk@siemens.com>
++ *
++ * AM6528-based (dual-core) IOT2050 Basic variant
++ * 1 GB RAM, no eMMC, main_uart0 on connector X30
++ */
++
++/dts-v1/;
++
++#include "k3-am65-iot2050-common.dtsi"
++
++/ {
++	compatible = "siemens,iot2050-basic", "ti,am654";
++	model = "SIMATIC IOT2050 Basic";
++
++	memory@80000000 {
++		device_type = "memory";
++		/* 1G RAM */
++		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
++	};
++
++	cpus {
++		cpu-map {
++			/delete-node/ cluster1;
++		};
++		/delete-node/ cpu@100;
++		/delete-node/ cpu@101;
++	};
++
++	/delete-node/ l2-cache1;
++};
++
++/* eMMC */
++&sdhci0 {
++	status = "disabled";
++};
++
++&main_pmx0 {
++	main_uart0_pins_default: main-uart0-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x01e4, PIN_INPUT,  0)  /* (AF11) UART0_RXD */
++			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)  /* (AE11) UART0_TXD */
++			AM65X_IOPAD(0x01ec, PIN_INPUT,  0)  /* (AG11) UART0_CTSn */
++			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)  /* (AD11) UART0_RTSn */
++			AM65X_IOPAD(0x0188, PIN_INPUT,  1)  /* (D25) UART0_DCDn */
++			AM65X_IOPAD(0x018c, PIN_INPUT,  1)  /* (B26) UART0_DSRn */
++			AM65X_IOPAD(0x0190, PIN_OUTPUT, 1)  /* (A24) UART0_DTRn */
++			AM65X_IOPAD(0x0194, PIN_INPUT,  1)  /* (E24) UART0_RIN */
++		>;
++	};
++};
++
++&main_uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_uart0_pins_default>;
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
+new file mode 100644
+index 000000000000..ec9617c13cdb
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
+@@ -0,0 +1,60 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2018-2021
++ *
++ * Authors:
++ *   Le Jin <le.jin@siemens.com>
++ *   Jan Kiszka <jan.kiszk@siemens.com>
++ *
++ * AM6548-based (quad-core) IOT2050 Advanced variant
++ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
++ */
++
++/dts-v1/;
++
++#include "k3-am65-iot2050-common.dtsi"
++
++/ {
++	compatible = "siemens,iot2050-advanced", "ti,am654";
++	model = "SIMATIC IOT2050 Advanced";
++
++	memory@80000000 {
++		device_type = "memory";
++		/* 2G RAM */
++		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
++	};
++};
++
++&main_pmx0 {
++	main_mmc0_pins_default: main-mmc0-pins-default {
++		pinctrl-single,pins = <
++			AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)  /* (B25) MMC0_CLK */
++			AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP,   0)  /* (B27) MMC0_CMD */
++			AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP,   0)  /* (A26) MMC0_DAT0 */
++			AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP,   0)  /* (E25) MMC0_DAT1 */
++			AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP,   0)  /* (C26) MMC0_DAT2 */
++			AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP,   0)  /* (A25) MMC0_DAT3 */
++			AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP,   0)  /* (E24) MMC0_DAT4 */
++			AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP,   0)  /* (A24) MMC0_DAT5 */
++			AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP,   0)  /* (B26) MMC0_DAT6 */
++			AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP,   0)  /* (D25) MMC0_DAT7 */
++			AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP,  7)  /* (B23) MMC0_SDWP */
++			AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP,   0)  /* (A23) MMC0_SDCD */
++			AM65X_IOPAD(0x01b0, PIN_INPUT,          0)  /* (C25) MMC0_DS */
++		>;
++	};
++};
++
++/* eMMC */
++&sdhci0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&main_mmc0_pins_default>;
++	bus-width = <8>;
++	non-removable;
++	ti,driver-strength-ohm = <50>;
++	disable-wp;
++};
++
++&main_uart0 {
++	status = "disabled";
++};

board/PSG/iot2050/files/patches-5.10/0011-arm64-dts-ti-k3-am65-j721e-am64-Map-the-dma-navigato.patch

@@ -0,0 +1,103 @@
+From 5b951155feb25553db32941e645d2fa95d7fa3e2 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Mon, 10 May 2021 09:54:29 -0500
+Subject: [PATCH] arm64: dts: ti: k3-am65|j721e|am64: Map the dma / navigator
+ subsystem via explicit ranges
+
+Instead of using empty ranges property, lets map explicitly the address
+range that is mapped onto the dma / navigator subsystems (navss/dmss).
+
+This is also exposed via the dtbs_check with dt-schema newer than
+2021.03 version by throwing out following:
+arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000: main-navss:
+{'type': 'object'} is not allowed for
+{'compatible': ['simple-mfd'], '#address-cells': [[2]], .....
+
+This has already been correctly done for J7200, however was missed for
+other k3 SoCs. Fix that oversight.
+
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Reviewed-by: Tero Kristo <kristo@kernel.org>
+Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
+Link: https://lore.kernel.org/r/20210510145429.8752-1-nm@ti.com
+[Jan: drop am64 bits]
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi        | 4 ++--
+ arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi         | 4 ++--
+ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi       | 4 ++--
+ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 4 ++--
+ 4 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index 6d2662588565..92f55840a08d 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -447,11 +447,11 @@ intr_main_gpio: interrupt-controller0 {
+ 		ti,interrupt-ranges = <0 392 32>;
+ 	};
+ 
+-	main-navss {
++	main_navss: bus@30800000 {
+ 		compatible = "simple-mfd";
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+-		ranges;
++		ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>;
+ 		dma-coherent;
+ 		dma-ranges;
+ 
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+index 0388c02c2203..f5b8ef2f5f77 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+@@ -116,11 +116,11 @@ adc {
+ 		};
+ 	};
+ 
+-	mcu-navss {
++	mcu_navss: bus@28380000 {
+ 		compatible = "simple-mfd";
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+-		ranges;
++		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
+ 		dma-coherent;
+ 		dma-ranges;
+ 
+diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+index 81fddd145b86..b85889ae50e1 100644
+--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+@@ -136,11 +136,11 @@ main_gpio_intr: interrupt-controller0 {
+ 		ti,interrupt-ranges = <8 392 56>;
+ 	};
+ 
+-	main-navss {
++	main_navss: bus@30000000 {
+ 		compatible = "simple-mfd";
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+-		ranges;
++		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
+ 		dma-coherent;
+ 		dma-ranges;
+ 
+diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+index e581cb1d87ee..d766c7fe02af 100644
+--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+@@ -249,11 +249,11 @@ adc {
+ 		};
+ 	};
+ 
+-	mcu-navss {
++	mcu_navss: bus@28380000 {
+ 		compatible = "simple-mfd";
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+-		ranges;
++		ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
+ 		dma-coherent;
+ 		dma-ranges;
+ 

board/PSG/iot2050/files/patches-5.10/0012-arm64-dts-ti-k3-Introduce-reg-definition-for-interru.patch

@@ -0,0 +1,163 @@
+From d331d6a1411dd7ad9f77985237b6b0e0a58b5255 Mon Sep 17 00:00:00 2001
+From: Nishanth Menon <nm@ti.com>
+Date: Tue, 11 May 2021 14:48:21 -0500
+Subject: [PATCH] arm64: dts: ti: k3*: Introduce reg definition for interrupt
+ routers
+
+Interrupt routers are memory mapped peripherals, that are organized
+in our dts bus hierarchy to closely represents the actual hardware
+behavior.
+
+However, without explicitly calling out the reg property, using
+2021.03+ dt-schema package, this exposes the following problem with
+dtbs_check:
+
+/arch/arm64/boot/dts/ti/k3-am654-base-board.dt.yaml: bus@100000:
+interrupt-controller0: {'type': 'object'} is not allowed for
+{'compatible': ['ti,sci-intr'], .....
+
+Even though we don't use interrupt router directly via memory mapped
+registers and have to use it via the system controller, the hardware
+block is memory mapped, so describe the base address in device tree.
+
+This is a valid, comprehensive description of hardware and permitted
+by the existing ti,sci-intr schema.
+
+Reviewed-by: Tero Kristo <kristo@kernel.org>
+Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/20210511194821.13919-1-nm@ti.com
+[Jan: drop am64 bits]
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi        | 6 ++++--
+ arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi      | 3 ++-
+ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi       | 6 ++++--
+ arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 3 ++-
+ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi       | 6 ++++--
+ arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 3 ++-
+ 6 files changed, 18 insertions(+), 9 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index 92f55840a08d..75afafdcee6f 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -436,8 +436,9 @@ usb1_phy: phy@4110000 {
+ 		#phy-cells = <0>;
+ 	};
+ 
+-	intr_main_gpio: interrupt-controller0 {
++	intr_main_gpio: interrupt-controller@a00000 {
+ 		compatible = "ti,sci-intr";
++		reg = <0x0 0x00a00000 0x0 0x400>;
+ 		ti,intr-trigger-type = <1>;
+ 		interrupt-controller;
+ 		interrupt-parent = <&gic500>;
+@@ -457,8 +458,9 @@ main_navss: bus@30800000 {
+ 
+ 		ti,sci-dev-id = <118>;
+ 
+-		intr_main_navss: interrupt-controller1 {
++		intr_main_navss: interrupt-controller@310e0000 {
+ 			compatible = "ti,sci-intr";
++			reg = <0x0 0x310e0000 0x0 0x2000>;
+ 			ti,intr-trigger-type = <4>;
+ 			interrupt-controller;
+ 			interrupt-parent = <&gic500>;
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+index ed42f13e7663..62a18b110c52 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+@@ -69,8 +69,9 @@ wkup_i2c0: i2c@42120000 {
+ 		power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ 	};
+ 
+-	intr_wkup_gpio: interrupt-controller2 {
++	intr_wkup_gpio: interrupt-controller@42200000 {
+ 		compatible = "ti,sci-intr";
++		reg = <0x42200000 0x200>;
+ 		ti,intr-trigger-type = <1>;
+ 		interrupt-controller;
+ 		interrupt-parent = <&gic500>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+index cb22e65d61ab..a0365890571e 100644
+--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+@@ -64,8 +64,9 @@ gic_its: msi-controller@1820000 {
+ 		};
+ 	};
+ 
+-	main_gpio_intr: interrupt-controller0 {
++	main_gpio_intr: interrupt-controller@a00000 {
+ 		compatible = "ti,sci-intr";
++		reg = <0x00 0x00a00000 0x00 0x800>;
+ 		ti,intr-trigger-type = <1>;
+ 		interrupt-controller;
+ 		interrupt-parent = <&gic500>;
+@@ -84,8 +85,9 @@ main_navss: bus@30000000 {
+ 		dma-coherent;
+ 		dma-ranges;
+ 
+-		main_navss_intr: interrupt-controller1 {
++		main_navss_intr: interrupt-controller@310e0000 {
+ 			compatible = "ti,sci-intr";
++			reg = <0x00 0x310e0000 0x00 0x4000>;
+ 			ti,intr-trigger-type = <4>;
+ 			interrupt-controller;
+ 			interrupt-parent = <&gic500>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+index eb2a78a53512..c4e63272fbdb 100644
+--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+@@ -96,8 +96,9 @@ mcu_uart0: serial@40a00000 {
+ 		clock-names = "fclk";
+ 	};
+ 
+-	wkup_gpio_intr: interrupt-controller2 {
++	wkup_gpio_intr: interrupt-controller@42200000 {
+ 		compatible = "ti,sci-intr";
++		reg = <0x00 0x42200000 0x00 0x400>;
+ 		ti,intr-trigger-type = <1>;
+ 		interrupt-controller;
+ 		interrupt-parent = <&gic500>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+index b85889ae50e1..6b377d93b121 100644
+--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+@@ -125,8 +125,9 @@ gic_its: msi-controller@1820000 {
+ 		};
+ 	};
+ 
+-	main_gpio_intr: interrupt-controller0 {
++	main_gpio_intr: interrupt-controller@a00000 {
+ 		compatible = "ti,sci-intr";
++		reg = <0x00 0x00a00000 0x00 0x800>;
+ 		ti,intr-trigger-type = <1>;
+ 		interrupt-controller;
+ 		interrupt-parent = <&gic500>;
+@@ -146,8 +147,9 @@ main_navss: bus@30000000 {
+ 
+ 		ti,sci-dev-id = <199>;
+ 
+-		main_navss_intr: interrupt-controller1 {
++		main_navss_intr: interrupt-controller@310e0000 {
+ 			compatible = "ti,sci-intr";
++			reg = <0x0 0x310e0000 0x0 0x4000>;
+ 			ti,intr-trigger-type = <4>;
+ 			interrupt-controller;
+ 			interrupt-parent = <&gic500>;
+diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+index d766c7fe02af..282bbdc359ac 100644
+--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+@@ -96,8 +96,9 @@ mcu_uart0: serial@40a00000 {
+ 		clock-names = "fclk";
+ 	};
+ 
+-	wkup_gpio_intr: interrupt-controller2 {
++	wkup_gpio_intr: interrupt-controller@42200000 {
+ 		compatible = "ti,sci-intr";
++		reg = <0x00 0x42200000 0x00 0x400>;
+ 		ti,intr-trigger-type = <1>;
+ 		interrupt-controller;
+ 		interrupt-parent = <&gic500>;

board/PSG/iot2050/files/patches-5.10/0013-mmc-sdhci_am654-Use-pm_runtime_resume_and_get-to-rep.patch

@@ -0,0 +1,35 @@
+From 861c9deeb47fc980c7dc498cb5342fbe3388eef1 Mon Sep 17 00:00:00 2001
+From: Tian Tao <tiantao6@hisilicon.com>
+Date: Fri, 21 May 2021 08:59:35 +0800
+Subject: [PATCH] mmc: sdhci_am654: Use pm_runtime_resume_and_get() to replace
+ open coding
+
+use pm_runtime_resume_and_get() to replace pm_runtime_get_sync and
+pm_runtime_put_noidle. this change is just to simplify the code, no
+actual functional changes.
+
+Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
+Link: https://lore.kernel.org/r/1621558775-31185-1-git-send-email-tiantao6@hisilicon.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+---
+ drivers/mmc/host/sdhci_am654.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
+index 24cd6d3dc647..4964509f2f3e 100644
+--- a/drivers/mmc/host/sdhci_am654.c
++++ b/drivers/mmc/host/sdhci_am654.c
+@@ -803,11 +803,9 @@ static int sdhci_am654_probe(struct platform_device *pdev)
+ 
+ 	/* Clocks are enabled using pm_runtime */
+ 	pm_runtime_enable(dev);
+-	ret = pm_runtime_get_sync(dev);
+-	if (ret < 0) {
+-		pm_runtime_put_noidle(dev);
++	ret = pm_runtime_resume_and_get(dev);
++	if (ret)
+ 		goto pm_runtime_disable;
+-	}
+ 
+ 	base = devm_platform_ioremap_resource(pdev, 1);
+ 	if (IS_ERR(base)) {

board/PSG/iot2050/files/patches-5.10/0014-arm64-dts-ti-k3-am65-iot2050-common-Disable-mailbox-.patch

@@ -0,0 +1,80 @@
+From 277d967daa126d8d9ddec365e1a5884ad82659c2 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 14 May 2021 16:20:16 -0500
+Subject: [PATCH] arm64: dts: ti: k3-am65-iot2050-common: Disable mailbox nodes
+
+There are no sub-mailbox devices defined currently for both the
+IOT2050 boards. These are usually dictated by the firmwares running
+on the R5F remote processors and the applications they provide.
+Defining the actual sub-mailboxes will also dictate the interrupts
+the clusters will use for interrupts on the Cortex-A53 cores.
+
+Disable all of the Mailbox clusters until the sub-mailboxes are
+defined and used. This fixes the warnings around the missing
+interrupts with the upcoming conversion of the OMAP Mailbox binding
+to YAML format.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/20210514212016.3153-1-s-anna@ti.com
+---
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 48 +++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index de763ca9251c..f4ec9ed52939 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -653,3 +653,51 @@ &pcie1_rc {
+ &pcie1_ep {
+ 	status = "disabled";
+ };
++
++&mailbox0_cluster0 {
++	status = "disabled";
++};
++
++&mailbox0_cluster1 {
++	status = "disabled";
++};
++
++&mailbox0_cluster2 {
++	status = "disabled";
++};
++
++&mailbox0_cluster3 {
++	status = "disabled";
++};
++
++&mailbox0_cluster4 {
++	status = "disabled";
++};
++
++&mailbox0_cluster5 {
++	status = "disabled";
++};
++
++&mailbox0_cluster6 {
++	status = "disabled";
++};
++
++&mailbox0_cluster7 {
++	status = "disabled";
++};
++
++&mailbox0_cluster8 {
++	status = "disabled";
++};
++
++&mailbox0_cluster9 {
++	status = "disabled";
++};
++
++&mailbox0_cluster10 {
++	status = "disabled";
++};
++
++&mailbox0_cluster11 {
++	status = "disabled";
++};

board/PSG/iot2050/files/patches-5.10/0015-arm64-dts-ti-k3-am65-Add-support-for-UHS-I-modes-in-.patch

@@ -0,0 +1,109 @@
+From e61c3b62700052b819dff35f7eb2114b61a39c31 Mon Sep 17 00:00:00 2001
+From: Aswath Govindraju <a-govindraju@ti.com>
+Date: Sat, 29 May 2021 09:07:49 +0530
+Subject: [PATCH] arm64: dts: ti: k3-am65: Add support for UHS-I modes in
+ MMCSD1 subsystem
+
+UHS-I speed modes are supported in AM65 S.R. 2.0 SoC[1].
+
+Add support by removing the no-1-8-v tag and including the voltage
+regulator device tree nodes for power cycling.
+
+However, the 4 bit interface of AM65 SR 1.0 cannot be supported at 3.3 V or
+1.8 V because of erratas i2025 and i2026 [2]. As the SD card is the primary
+boot mode for development usecases, continue to enable SD card and disable
+UHS-I modes in it to minimize any ageing issues happening because of
+erratas.
+
+k3-am6528-iot2050-basic and k3-am6548-iot2050-advanced boards use S.R. 1.0
+version of AM65 SoC. Therefore, add no-1-8-v in sdhci1 device tree node of
+the common iot2050 device tree file.
+
+[1] - https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf, section 12.3.6.1.1
+[2] - https://www.ti.com/lit/er/sprz452e/sprz452e.pdf
+
+Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
+Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/20210529033749.6250-1-a-govindraju@ti.com
+---
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   |  1 +
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi      |  1 -
+ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 33 +++++++++++++++++++
+ 3 files changed, 34 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index f4ec9ed52939..d90abda1de84 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -555,6 +555,7 @@ &sdhci1 {
+ 	pinctrl-0 = <&main_mmc1_pins_default>;
+ 	ti,driver-strength-ohm = <50>;
+ 	disable-wp;
++	no-1-8-v;
+ };
+ 
+ &usb0 {
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index 75afafdcee6f..c288d03da908 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -304,7 +304,6 @@ sdhci1: mmc@4fa0000 {
+ 		ti,otap-del-sel = <0x2>;
+ 		ti,trm-icp = <0x8>;
+ 		dma-coherent;
+-		no-1-8-v;
+ 	};
+ 
+ 	scm_conf: scm-conf@100000 {
+diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+index 8c082af489f5..fea6a8243d75 100644
+--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
++++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+@@ -60,6 +60,38 @@ clk_ov5640_fixed: clock {
+ 		#clock-cells = <0>;
+ 		clock-frequency = <24000000>;
+ 	};
++
++	evm_12v0: fixedregulator-evm12v0 {
++		/* main supply */
++		compatible = "regulator-fixed";
++		regulator-name = "evm_12v0";
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++		regulator-always-on;
++		regulator-boot-on;
++	};
++
++	vcc3v3_io: fixedregulator-vcc3v3io {
++		/* Output of TPS54334 */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_io";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&evm_12v0>;
++	};
++
++	vdd_mmc1_sd: fixedregulator-sd {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd_mmc1_sd";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++		enable-active-high;
++		vin-supply = <&vcc3v3_io>;
++		gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
++	};
+ };
+ 
+ &wkup_pmx0 {
+@@ -319,6 +351,7 @@ &sdhci0 {
+  * disable sdhci1
+  */
+ &sdhci1 {
++	vmmc-supply = <&vdd_mmc1_sd>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&main_mmc1_pins_default>;
+ 	ti,driver-strength-ohm = <50>;

board/PSG/iot2050/files/patches-5.10/0016-arm64-dts-ti-k3-am65-main-Add-ICSSG-MDIO-nodes.patch

@@ -0,0 +1,126 @@
+From fa1a97a8f5be987b5db17ac0f18c26a80a4dddd3 Mon Sep 17 00:00:00 2001
+From: Roger Quadros <rogerq@ti.com>
+Date: Tue, 1 Jun 2021 10:00:31 -0500
+Subject: [PATCH] arm64: dts: ti: k3-am65-main: Add ICSSG MDIO nodes
+
+The ICSSGs on K3 AM65x SoCs contain an MDIO controller that can
+be used to control external PHYs associated with the Industrial
+Ethernet peripherals within each ICSSG instance. The MDIO module
+used within the ICSSG is similar to the MDIO Controller used
+in TI Davinci SoCs. A bus frequency of 1 MHz is chosen for the
+MDIO operations.
+
+The nodes are added and enabled in the common k3-am65-main.dtsi
+file by default, and disabled in the existing AM65 board dts
+files. These nodes need pinctrl lines, and so should be enabled
+only on boards where they are actually wired and pinned out for
+ICSSG Ethernet. Any new board dts file should disable these if
+they are not sure.
+
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+[s-anna@ti.com: move the disabled status to board dts files]
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/20210601150032.11432-2-s-anna@ti.com
+---
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 12 ++++++++
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi      | 30 +++++++++++++++++++
+ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ++++++++
+ 3 files changed, 54 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index d90abda1de84..8c6b538c53f3 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -702,3 +702,15 @@ &mailbox0_cluster10 {
+ &mailbox0_cluster11 {
+ 	status = "disabled";
+ };
++
++&icssg0_mdio {
++	status = "disabled";
++};
++
++&icssg1_mdio {
++	status = "disabled";
++};
++
++&icssg2_mdio {
++	status = "disabled";
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index c288d03da908..a506a24bd9c2 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -1054,6 +1054,16 @@ tx_pru0_1: txpru@c000 {
+ 			reg-names = "iram", "control", "debug";
+ 			firmware-name = "am65x-txpru0_1-fw";
+ 		};
++
++		icssg0_mdio: mdio@32400 {
++			compatible = "ti,davinci_mdio";
++			reg = <0x32400 0x100>;
++			clocks = <&k3_clks 62 3>;
++			clock-names = "fck";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			bus_freq = <1000000>;
++		};
+ 	};
+ 
+ 	icssg1: icssg@b100000 {
+@@ -1185,6 +1195,16 @@ tx_pru1_1: txpru@c000 {
+ 			reg-names = "iram", "control", "debug";
+ 			firmware-name = "am65x-txpru1_1-fw";
+ 		};
++
++		icssg1_mdio: mdio@32400 {
++			compatible = "ti,davinci_mdio";
++			reg = <0x32400 0x100>;
++			clocks = <&k3_clks 63 3>;
++			clock-names = "fck";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			bus_freq = <1000000>;
++		};
+ 	};
+ 
+ 	icssg2: icssg@b200000 {
+@@ -1316,5 +1336,15 @@ tx_pru2_1: txpru@c000 {
+ 			reg-names = "iram", "control", "debug";
+ 			firmware-name = "am65x-txpru2_1-fw";
+ 		};
++
++		icssg2_mdio: mdio@32400 {
++			compatible = "ti,davinci_mdio";
++			reg = <0x32400 0x100>;
++			clocks = <&k3_clks 64 3>;
++			clock-names = "fck";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			bus_freq = <1000000>;
++		};
+ 	};
+ };
+diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+index fea6a8243d75..b47fc2a1e59d 100644
+--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
++++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+@@ -535,3 +535,15 @@ &mcasp2 {
+ &dss {
+ 	status = "disabled";
+ };
++
++&icssg0_mdio {
++	status = "disabled";
++};
++
++&icssg1_mdio {
++	status = "disabled";
++};
++
++&icssg2_mdio {
++	status = "disabled";
++};

board/PSG/iot2050/files/patches-5.10/0017-arm64-dts-ti-iot2050-Configure-r5f-cluster-on-basic-.patch

@@ -0,0 +1,29 @@
+From 6f17bb476e05d69a1d950494c1b3e6db7342dc24 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Wed, 2 Jun 2021 08:56:15 +0200
+Subject: [PATCH] arm64: dts: ti: iot2050: Configure r5f cluster on basic
+ variant in split mode
+
+Lockstep mode is not supported here. So turn it off to avoid warnings
+during startup.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/3a241e50-80a3-992a-2445-345c629d7895@siemens.com
+---
+ arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+index 4f7e3f2a6265..94bb5dd39122 100644
+--- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
++++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+@@ -59,3 +59,8 @@ &main_uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&main_uart0_pins_default>;
+ };
++
++&mcu_r5fss0 {
++	/* lock-step mode not supported on this board */
++	ti,cluster-mode = <0>;
++};

board/PSG/iot2050/files/patches-5.10/0018-arm64-dts-ti-am65-align-ti-pindir-d0-out-d1-in-prope.patch

@@ -0,0 +1,47 @@
+From 6ade503971c9bbd900e12dc0a38197289654efaf Mon Sep 17 00:00:00 2001
+From: Aswath Govindraju <a-govindraju@ti.com>
+Date: Tue, 8 Jun 2021 10:44:13 +0530
+Subject: [PATCH] arm64: dts: ti: am65: align ti,pindir-d0-out-d1-in property
+ with dt-shema
+
+ti,pindir-d0-out-d1-in property is expected to be of type boolean.
+Therefore, fix the property accordingly.
+
+Fixes: e180f76d0641 ("arm64: dts: ti: Add support for Siemens IOT2050 boards")
+Fixes: 5da94b50475a ("arm64: dts: ti: k3-am654: Enable main domain McSPI0")
+Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
+Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
+Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/20210608051414.14873-2-a-govindraju@ti.com
+---
+ arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 +-
+ arch/arm64/boot/dts/ti/k3-am654-base-board.dts     | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index 8c6b538c53f3..1008e9162ba2 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -576,7 +576,7 @@ &mcu_spi0 {
+ 
+ 	#address-cells = <1>;
+ 	#size-cells= <0>;
+-	ti,pindir-d0-out-d1-in = <1>;
++	ti,pindir-d0-out-d1-in;
+ };
+ 
+ &tscadc0 {
+diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+index b47fc2a1e59d..56dc855a5f13 100644
+--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
++++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+@@ -323,7 +323,7 @@ &main_spi0 {
+ 	pinctrl-0 = <&main_spi0_pins_default>;
+ 	#address-cells = <1>;
+ 	#size-cells= <0>;
+-	ti,pindir-d0-out-d1-in = <1>;
++	ti,pindir-d0-out-d1-in;
+ 
+ 	flash@0{
+ 		compatible = "jedec,spi-nor";

board/PSG/iot2050/files/patches-5.10/0019-firmware-ti_sci-rm-Add-support-for-tx_tdtype-paramet.patch

@@ -0,0 +1,87 @@
+From 7288ba471be4e1025c286d5673b3a177409316a0 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:02 -0700
+Subject: [PATCH] firmware: ti_sci: rm: Add support for tx_tdtype parameter for
+ tx channel
+
+The system controller's resource manager have support for configuring the
+TDTYPE of TCHAN_CFG register on j721e.
+With this parameter the teardown completion can be controlled:
+TDTYPE == 0: Return without waiting for peer to complete the teardown
+TDTYPE == 1: Wait for peer to complete the teardown
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Tero Kristo <t-kristo@ti.com>
+Tested-by: Keerthy <j-keerthy@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 1 +
+ drivers/firmware/ti_sci.h              | 7 +++++++
+ include/linux/soc/ti/ti_sci_protocol.h | 2 ++
+ 3 files changed, 10 insertions(+)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index 896f53ec7857..65a8c2e82093 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -2362,6 +2362,7 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle,
+ 	req->fdepth = params->fdepth;
+ 	req->tx_sched_priority = params->tx_sched_priority;
+ 	req->tx_burst_size = params->tx_burst_size;
++	req->tx_tdtype = params->tx_tdtype;
+ 
+ 	ret = ti_sci_do_xfer(info, xfer);
+ 	if (ret) {
+diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
+index 57cd04062994..dca19ca5fc49 100644
+--- a/drivers/firmware/ti_sci.h
++++ b/drivers/firmware/ti_sci.h
+@@ -910,6 +910,7 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
+  *   12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
+  *   13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
+  *   14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
++ *   15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
+  *
+  * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
+  *
+@@ -973,6 +974,11 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
+  *
+  * @tx_burst_size: UDMAP transmit channel burst size configuration to be
+  * programmed into the tx_burst_size field of the TCHAN_TCFG register.
++ *
++ * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
++ * programmed into the tdtype field of the TCHAN_TCFG register:
++ * 0 - Return immediately
++ * 1 - Wait for completion message from remote peer
+  */
+ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
+ 	struct ti_sci_msg_hdr hdr;
+@@ -994,6 +1000,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
+ 	u16 fdepth;
+ 	u8 tx_sched_priority;
+ 	u8 tx_burst_size;
++	u8 tx_tdtype;
+ } __packed;
+ 
+ /**
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index b1af87330f86..fece890e1635 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -345,6 +345,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID        BIT(11)
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
++#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID            BIT(15)
+ 	u16 nav_id;
+ 	u16 index;
+ 	u8 tx_pause_on_err;
+@@ -362,6 +363,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
+ 	u16 fdepth;
+ 	u8 tx_sched_priority;
+ 	u8 tx_burst_size;
++	u8 tx_tdtype;
+ };
+ 
+ /**

board/PSG/iot2050/files/patches-5.10/0020-firmware-ti_sci-Use-struct-ti_sci_resource_desc-in-g.patch

@@ -0,0 +1,178 @@
+From 654db83468e05a905e9205a901fc99b894ee05d3 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:03 -0700
+Subject: [PATCH] firmware: ti_sci: Use struct ti_sci_resource_desc in
+ get_range ops
+
+Use the ti_sci_resource_desc directly and update it's start and num members
+directly instead of requiring individual parameters for them.
+
+This will allow easy extension of the RM parameters without changing API.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 32 ++++++++++++--------------
+ include/linux/soc/ti/ti_sci_protocol.h | 32 +++++++++++++-------------
+ 2 files changed, 31 insertions(+), 33 deletions(-)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index 65a8c2e82093..7a777e91ce3e 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -1703,14 +1703,14 @@ static int ti_sci_cmd_core_reboot(const struct ti_sci_handle *handle)
+  * @subtype:		Resource assignment subtype that is being requested
+  *			from the given device.
+  * @s_host:		Host processor ID to which the resources are allocated
+- * @range_start:	Start index of the resource range
+- * @range_num:		Number of resources in the range
++ * @desc:		Pointer to ti_sci_resource_desc to be updated with the
++ *			resource range start index and number of resources
+  *
+  * Return: 0 if all went fine, else return appropriate error.
+  */
+ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
+ 				     u32 dev_id, u8 subtype, u8 s_host,
+-				     u16 *range_start, u16 *range_num)
++				     struct ti_sci_resource_desc *desc)
+ {
+ 	struct ti_sci_msg_resp_get_resource_range *resp;
+ 	struct ti_sci_msg_req_get_resource_range *req;
+@@ -1721,7 +1721,7 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
+ 
+ 	if (IS_ERR(handle))
+ 		return PTR_ERR(handle);
+-	if (!handle)
++	if (!handle || !desc)
+ 		return -EINVAL;
+ 
+ 	info = handle_to_ti_sci_info(handle);
+@@ -1754,8 +1754,8 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
+ 	} else if (!resp->range_start && !resp->range_num) {
+ 		ret = -ENODEV;
+ 	} else {
+-		*range_start = resp->range_start;
+-		*range_num = resp->range_num;
++		desc->start = resp->range_start;
++		desc->num = resp->range_num;
+ 	};
+ 
+ fail:
+@@ -1771,18 +1771,18 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
+  * @dev_id:		TISCI device ID.
+  * @subtype:		Resource assignment subtype that is being requested
+  *			from the given device.
+- * @range_start:	Start index of the resource range
+- * @range_num:		Number of resources in the range
++ * @desc:		Pointer to ti_sci_resource_desc to be updated with the
++ *			resource range start index and number of resources
+  *
+  * Return: 0 if all went fine, else return appropriate error.
+  */
+ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle,
+ 					 u32 dev_id, u8 subtype,
+-					 u16 *range_start, u16 *range_num)
++					 struct ti_sci_resource_desc *desc)
+ {
+ 	return ti_sci_get_resource_range(handle, dev_id, subtype,
+ 					 TI_SCI_IRQ_SECONDARY_HOST_INVALID,
+-					 range_start, range_num);
++					 desc);
+ }
+ 
+ /**
+@@ -1793,18 +1793,17 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle,
+  * @subtype:		Resource assignment subtype that is being requested
+  *			from the given device.
+  * @s_host:		Host processor ID to which the resources are allocated
+- * @range_start:	Start index of the resource range
+- * @range_num:		Number of resources in the range
++ * @desc:		Pointer to ti_sci_resource_desc to be updated with the
++ *			resource range start index and number of resources
+  *
+  * Return: 0 if all went fine, else return appropriate error.
+  */
+ static
+ int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle,
+ 					     u32 dev_id, u8 subtype, u8 s_host,
+-					     u16 *range_start, u16 *range_num)
++					     struct ti_sci_resource_desc *desc)
+ {
+-	return ti_sci_get_resource_range(handle, dev_id, subtype, s_host,
+-					 range_start, range_num);
++	return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, desc);
+ }
+ 
+ /**
+@@ -3243,8 +3242,7 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
+ 	for (i = 0; i < res->sets; i++) {
+ 		ret = handle->ops.rm_core_ops.get_range(handle, dev_id,
+ 							sub_types[i],
+-							&res->desc[i].start,
+-							&res->desc[i].num);
++							&res->desc[i]);
+ 		if (ret) {
+ 			dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n",
+ 				dev_id, sub_types[i]);
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index fece890e1635..19b90545edd8 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -195,6 +195,18 @@ struct ti_sci_clk_ops {
+ 			u64 *current_freq);
+ };
+ 
++/**
++ * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
++ * @start:	Start index of the resource.
++ * @num:	Number of resources.
++ * @res_map:	Bitmap to manage the allocation of these resources.
++ */
++struct ti_sci_resource_desc {
++	u16 start;
++	u16 num;
++	unsigned long *res_map;
++};
++
+ /**
+  * struct ti_sci_rm_core_ops - Resource management core operations
+  * @get_range:		Get a range of resources belonging to ti sci host.
+@@ -209,15 +221,15 @@ struct ti_sci_clk_ops {
+  * - dev_id:	TISCI device ID.
+  * - subtype:	Resource assignment subtype that is being requested
+  *		from the given device.
+- * - range_start:	Start index of the resource range
+- * - range_end:		Number of resources in the range
++ * - desc:	Pointer to ti_sci_resource_desc to be updated with the resource
++ *		range start index and number of resources
+  */
+ struct ti_sci_rm_core_ops {
+ 	int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
+-			 u8 subtype, u16 *range_start, u16 *range_num);
++			 u8 subtype, struct ti_sci_resource_desc *desc);
+ 	int (*get_range_from_shost)(const struct ti_sci_handle *handle,
+ 				    u32 dev_id, u8 subtype, u8 s_host,
+-				    u16 *range_start, u16 *range_num);
++				    struct ti_sci_resource_desc *desc);
+ };
+ 
+ #define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT		0
+@@ -522,18 +534,6 @@ struct ti_sci_handle {
+ 
+ #define TI_SCI_RESOURCE_NULL	0xffff
+ 
+-/**
+- * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
+- * @start:	Start index of the resource.
+- * @num:	Number of resources.
+- * @res_map:	Bitmap to manage the allocation of these resources.
+- */
+-struct ti_sci_resource_desc {
+-	u16 start;
+-	u16 num;
+-	unsigned long *res_map;
+-};
+-
+ /**
+  * struct ti_sci_resource - Structure representing a resource assigned
+  *			    to a device.

board/PSG/iot2050/files/patches-5.10/0021-firmware-ti_sci-rm-Add-support-for-second-resource-r.patch

@@ -0,0 +1,174 @@
+From 326b93e726ab4a9850ead2a177530abcd47e4cf7 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:03 -0700
+Subject: [PATCH] firmware: ti_sci: rm: Add support for second resource range
+
+Sysfw added support for a second range in the resource range API to be able
+to describe complex allocations mainly for DMA channels.
+
+Update the ti_sci part to consider the second range as well.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 48 +++++++++++++++++---------
+ drivers/firmware/ti_sci.h              |  8 +++--
+ include/linux/soc/ti/ti_sci_protocol.h |  8 +++--
+ 3 files changed, 43 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index 7a777e91ce3e..2793bb923881 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -1751,11 +1751,14 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle,
+ 
+ 	if (!ti_sci_is_response_ack(resp)) {
+ 		ret = -ENODEV;
+-	} else if (!resp->range_start && !resp->range_num) {
++	} else if (!resp->range_num && !resp->range_num_sec) {
++		/* Neither of the two resource range is valid */
+ 		ret = -ENODEV;
+ 	} else {
+ 		desc->start = resp->range_start;
+ 		desc->num = resp->range_num;
++		desc->start_sec = resp->range_start_sec;
++		desc->num_sec = resp->range_num_sec;
+ 	};
+ 
+ fail:
+@@ -3157,12 +3160,18 @@ u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
+ 
+ 	raw_spin_lock_irqsave(&res->lock, flags);
+ 	for (set = 0; set < res->sets; set++) {
+-		free_bit = find_first_zero_bit(res->desc[set].res_map,
+-					       res->desc[set].num);
+-		if (free_bit != res->desc[set].num) {
+-			set_bit(free_bit, res->desc[set].res_map);
++		struct ti_sci_resource_desc *desc = &res->desc[set];
++		int res_count = desc->num + desc->num_sec;
++
++		free_bit = find_first_zero_bit(desc->res_map, res_count);
++		if (free_bit != res_count) {
++			set_bit(free_bit, desc->res_map);
+ 			raw_spin_unlock_irqrestore(&res->lock, flags);
+-			return res->desc[set].start + free_bit;
++
++			if (desc->num && free_bit < desc->num)
++				return desc->start + free_bit;
++			else
++				return desc->start_sec + free_bit;
+ 		}
+ 	}
+ 	raw_spin_unlock_irqrestore(&res->lock, flags);
+@@ -3183,10 +3192,14 @@ void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
+ 
+ 	raw_spin_lock_irqsave(&res->lock, flags);
+ 	for (set = 0; set < res->sets; set++) {
+-		if (res->desc[set].start <= id &&
+-		    (res->desc[set].num + res->desc[set].start) > id)
+-			clear_bit(id - res->desc[set].start,
+-				  res->desc[set].res_map);
++		struct ti_sci_resource_desc *desc = &res->desc[set];
++
++		if (desc->num && desc->start <= id &&
++		    (desc->start + desc->num) > id)
++			clear_bit(id - desc->start, desc->res_map);
++		else if (desc->num_sec && desc->start_sec <= id &&
++			 (desc->start_sec + desc->num_sec) > id)
++			clear_bit(id - desc->start_sec, desc->res_map);
+ 	}
+ 	raw_spin_unlock_irqrestore(&res->lock, flags);
+ }
+@@ -3203,7 +3216,7 @@ u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
+ 	u32 set, count = 0;
+ 
+ 	for (set = 0; set < res->sets; set++)
+-		count += res->desc[set].num;
++		count += res->desc[set].num + res->desc[set].num_sec;
+ 
+ 	return count;
+ }
+@@ -3227,7 +3240,7 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
+ {
+ 	struct ti_sci_resource *res;
+ 	bool valid_set = false;
+-	int i, ret;
++	int i, ret, res_count;
+ 
+ 	res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL);
+ 	if (!res)
+@@ -3246,18 +3259,19 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle,
+ 		if (ret) {
+ 			dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n",
+ 				dev_id, sub_types[i]);
+-			res->desc[i].start = 0;
+-			res->desc[i].num = 0;
++			memset(&res->desc[i], 0, sizeof(res->desc[i]));
+ 			continue;
+ 		}
+ 
+-		dev_dbg(dev, "dev = %d, subtype = %d, start = %d, num = %d\n",
++		dev_dbg(dev, "dev/sub_type: %d/%d, start/num: %d/%d | %d/%d\n",
+ 			dev_id, sub_types[i], res->desc[i].start,
+-			res->desc[i].num);
++			res->desc[i].num, res->desc[i].start_sec,
++			res->desc[i].num_sec);
+ 
+ 		valid_set = true;
++		res_count = res->desc[i].num + res->desc[i].num_sec;
+ 		res->desc[i].res_map =
+-			devm_kzalloc(dev, BITS_TO_LONGS(res->desc[i].num) *
++			devm_kzalloc(dev, BITS_TO_LONGS(res_count) *
+ 				     sizeof(*res->desc[i].res_map), GFP_KERNEL);
+ 		if (!res->desc[i].res_map)
+ 			return ERR_PTR(-ENOMEM);
+diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
+index dca19ca5fc49..4d980eb592c4 100644
+--- a/drivers/firmware/ti_sci.h
++++ b/drivers/firmware/ti_sci.h
+@@ -574,8 +574,10 @@ struct ti_sci_msg_req_get_resource_range {
+ /**
+  * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
+  * @hdr:		Generic Header
+- * @range_start:	Start index of the resource range.
+- * @range_num:		Number of resources in the range.
++ * @range_start:	Start index of the first resource range.
++ * @range_num:		Number of resources in the first range.
++ * @range_start_sec:	Start index of the second resource range.
++ * @range_num_sec:	Number of resources in the second range.
+  *
+  * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
+  */
+@@ -583,6 +585,8 @@ struct ti_sci_msg_resp_get_resource_range {
+ 	struct ti_sci_msg_hdr hdr;
+ 	u16 range_start;
+ 	u16 range_num;
++	u16 range_start_sec;
++	u16 range_num_sec;
+ } __packed;
+ 
+ /**
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index 19b90545edd8..2cd563c7328c 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -197,13 +197,17 @@ struct ti_sci_clk_ops {
+ 
+ /**
+  * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
+- * @start:	Start index of the resource.
+- * @num:	Number of resources.
++ * @start:	Start index of the first resource range.
++ * @num:	Number of resources in the first range.
++ * @start_sec:	Start index of the second resource range.
++ * @num_sec:	Number of resources in the second range.
+  * @res_map:	Bitmap to manage the allocation of these resources.
+  */
+ struct ti_sci_resource_desc {
+ 	u16 start;
+ 	u16 num;
++	u16 start_sec;
++	u16 num_sec;
+ 	unsigned long *res_map;
+ };
+ 

board/PSG/iot2050/files/patches-5.10/0022-soc-ti-ti_sci_inta_msi-Add-support-for-second-range-.patch

@@ -0,0 +1,37 @@
+From 74a16f0f4302803e576a23e5d6d32b889e2cbb24 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:04 -0700
+Subject: [PATCH] soc: ti: ti_sci_inta_msi: Add support for second range in
+ resource ranges
+
+Allocate MSI entries for both first and second range if they are valid
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/ti_sci_inta_msi.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/soc/ti/ti_sci_inta_msi.c b/drivers/soc/ti/ti_sci_inta_msi.c
+index 0eb9462f609e..a1d9c027022a 100644
+--- a/drivers/soc/ti/ti_sci_inta_msi.c
++++ b/drivers/soc/ti/ti_sci_inta_msi.c
+@@ -89,6 +89,18 @@ static int ti_sci_inta_msi_alloc_descs(struct device *dev,
+ 			list_add_tail(&msi_desc->list, dev_to_msi_list(dev));
+ 			count++;
+ 		}
++		for (i = 0; i < res->desc[set].num_sec; i++) {
++			msi_desc = alloc_msi_entry(dev, 1, NULL);
++			if (!msi_desc) {
++				ti_sci_inta_msi_free_descs(dev);
++				return -ENOMEM;
++			}
++
++			msi_desc->inta.dev_index = res->desc[set].start_sec + i;
++			INIT_LIST_HEAD(&msi_desc->list);
++			list_add_tail(&msi_desc->list, dev_to_msi_list(dev));
++			count++;
++		}
+ 	}
+ 
+ 	return count;

board/PSG/iot2050/files/patches-5.10/0023-firmware-ti_sci-rm-Add-support-for-extended_ch_type-.patch

@@ -0,0 +1,92 @@
+From 66e3b73e7f8ff8110afc10a8bcc23458565e49d0 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:05 -0700
+Subject: [PATCH] firmware: ti_sci: rm: Add support for extended_ch_type for tx
+ channel
+
+Sysfw added 'extended_ch_type' to the tx_ch_cfg_req message which should be
+used when BCDMA block copy channels are configured:
+extended_ch_type = 0 : the channel is split tx channel (tchan)
+extended_ch_type = 1 : the channel is block copy channel (bchan)
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 1 +
+ drivers/firmware/ti_sci.h              | 6 ++++++
+ include/linux/soc/ti/ti_sci_protocol.h | 5 +++++
+ 3 files changed, 12 insertions(+)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index 2793bb923881..0dd3fbb4f964 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -2365,6 +2365,7 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle,
+ 	req->tx_sched_priority = params->tx_sched_priority;
+ 	req->tx_burst_size = params->tx_burst_size;
+ 	req->tx_tdtype = params->tx_tdtype;
++	req->extended_ch_type = params->extended_ch_type;
+ 
+ 	ret = ti_sci_do_xfer(info, xfer);
+ 	if (ret) {
+diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
+index 4d980eb592c4..ca15d8f1f8de 100644
+--- a/drivers/firmware/ti_sci.h
++++ b/drivers/firmware/ti_sci.h
+@@ -915,6 +915,7 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
+  *   13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
+  *   14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
+  *   15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
++ *   16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
+  *
+  * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
+  *
+@@ -983,6 +984,10 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
+  * programmed into the tdtype field of the TCHAN_TCFG register:
+  * 0 - Return immediately
+  * 1 - Wait for completion message from remote peer
++ *
++ * @extended_ch_type: Valid for BCDMA.
++ * 0 - the channel is split tx channel (tchan)
++ * 1 - the channel is block copy channel (bchan)
+  */
+ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
+ 	struct ti_sci_msg_hdr hdr;
+@@ -1005,6 +1010,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
+ 	u8 tx_sched_priority;
+ 	u8 tx_burst_size;
+ 	u8 tx_tdtype;
++	u8 extended_ch_type;
+ } __packed;
+ 
+ /**
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index 2cd563c7328c..a090b72a3362 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -336,6 +336,9 @@ struct ti_sci_rm_psil_ops {
+ #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES	2
+ #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES	3
+ 
++#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN		0
++#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN		1
++
+ /* UDMAP TX/RX channel valid_params common declarations */
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID		BIT(0)
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID                BIT(1)
+@@ -362,6 +365,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID      BIT(12)
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID            BIT(13)
+ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID            BIT(15)
++#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID	BIT(16)
+ 	u16 nav_id;
+ 	u16 index;
+ 	u8 tx_pause_on_err;
+@@ -380,6 +384,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg {
+ 	u8 tx_sched_priority;
+ 	u8 tx_burst_size;
+ 	u8 tx_tdtype;
++	u8 extended_ch_type;
+ };
+ 
+ /**

board/PSG/iot2050/files/patches-5.10/0024-firmware-ti_sci-rm-Remove-ring_get_config-support.patch

@@ -0,0 +1,201 @@
+From 031eb08678d355c623d6632ae13f8f38ef0910f1 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:05 -0700
+Subject: [PATCH] firmware: ti_sci: rm: Remove ring_get_config support
+
+The ring_get_cfg (0x1111 message) is not used and it is not supported by
+sysfw for a long time.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 80 --------------------------
+ drivers/firmware/ti_sci.h              | 44 --------------
+ include/linux/soc/ti/ti_sci_protocol.h |  6 --
+ 3 files changed, 130 deletions(-)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index 0dd3fbb4f964..0b801e67e672 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -2119,85 +2119,6 @@ static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
+ 	return ret;
+ }
+ 
+-/**
+- * ti_sci_cmd_ring_get_config() - get RA ring configuration
+- * @handle:	Pointer to TI SCI handle.
+- * @nav_id:	Device ID of Navigator Subsystem from which the ring is
+- *		allocated
+- * @index:	Ring index
+- * @addr_lo:	Returns ring's base address lo 32 bits
+- * @addr_hi:	Returns ring's base address hi 32 bits
+- * @count:	Returns number of ring elements
+- * @mode:	Returns mode of the ring
+- * @size:	Returns ring element size
+- * @order_id:	Returns ring's bus order ID
+- *
+- * Return: 0 if all went well, else returns appropriate error value.
+- *
+- * See @ti_sci_msg_rm_ring_get_cfg_req for more info.
+- */
+-static int ti_sci_cmd_ring_get_config(const struct ti_sci_handle *handle,
+-				      u32 nav_id, u32 index, u8 *mode,
+-				      u32 *addr_lo, u32 *addr_hi,
+-				      u32 *count, u8 *size, u8 *order_id)
+-{
+-	struct ti_sci_msg_rm_ring_get_cfg_resp *resp;
+-	struct ti_sci_msg_rm_ring_get_cfg_req *req;
+-	struct ti_sci_xfer *xfer;
+-	struct ti_sci_info *info;
+-	struct device *dev;
+-	int ret = 0;
+-
+-	if (IS_ERR_OR_NULL(handle))
+-		return -EINVAL;
+-
+-	info = handle_to_ti_sci_info(handle);
+-	dev = info->dev;
+-
+-	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_GET_CFG,
+-				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+-				   sizeof(*req), sizeof(*resp));
+-	if (IS_ERR(xfer)) {
+-		ret = PTR_ERR(xfer);
+-		dev_err(dev,
+-			"RM_RA:Message get config failed(%d)\n", ret);
+-		return ret;
+-	}
+-	req = (struct ti_sci_msg_rm_ring_get_cfg_req *)xfer->xfer_buf;
+-	req->nav_id = nav_id;
+-	req->index = index;
+-
+-	ret = ti_sci_do_xfer(info, xfer);
+-	if (ret) {
+-		dev_err(dev, "RM_RA:Mbox get config send fail %d\n", ret);
+-		goto fail;
+-	}
+-
+-	resp = (struct ti_sci_msg_rm_ring_get_cfg_resp *)xfer->xfer_buf;
+-
+-	if (!ti_sci_is_response_ack(resp)) {
+-		ret = -ENODEV;
+-	} else {
+-		if (mode)
+-			*mode = resp->mode;
+-		if (addr_lo)
+-			*addr_lo = resp->addr_lo;
+-		if (addr_hi)
+-			*addr_hi = resp->addr_hi;
+-		if (count)
+-			*count = resp->count;
+-		if (size)
+-			*size = resp->size;
+-		if (order_id)
+-			*order_id = resp->order_id;
+-	};
+-
+-fail:
+-	ti_sci_put_one_xfer(&info->minfo, xfer);
+-	dev_dbg(dev, "RM_RA:get config ring %u ret:%d\n", index, ret);
+-	return ret;
+-}
+-
+ /**
+  * ti_sci_cmd_rm_psil_pair() - Pair PSI-L source to destination thread
+  * @handle:	Pointer to TI SCI handle.
+@@ -2926,7 +2847,6 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
+ 	iops->free_event_map = ti_sci_cmd_free_event_map;
+ 
+ 	rops->config = ti_sci_cmd_ring_config;
+-	rops->get_config = ti_sci_cmd_ring_get_config;
+ 
+ 	psilops->pair = ti_sci_cmd_rm_psil_pair;
+ 	psilops->unpair = ti_sci_cmd_rm_psil_unpair;
+diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
+index ca15d8f1f8de..1cdf918be861 100644
+--- a/drivers/firmware/ti_sci.h
++++ b/drivers/firmware/ti_sci.h
+@@ -49,7 +49,6 @@
+ #define TI_SCI_MSG_RM_RING_RECONFIG		0x1102
+ #define TI_SCI_MSG_RM_RING_RESET		0x1103
+ #define TI_SCI_MSG_RM_RING_CFG			0x1110
+-#define TI_SCI_MSG_RM_RING_GET_CFG		0x1111
+ 
+ /* PSI-L requests */
+ #define TI_SCI_MSG_RM_PSIL_PAIR			0x1280
+@@ -687,49 +686,6 @@ struct ti_sci_msg_rm_ring_cfg_req {
+ 	u8 order_id;
+ } __packed;
+ 
+-/**
+- * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
+- *
+- * Gets the configuration of the non-real-time register fields of a ring.  The
+- * host, or a supervisor of the host, who owns the ring must be the requesting
+- * host.  The values of the non-real-time registers are returned in
+- * @ti_sci_msg_rm_ring_get_cfg_resp.
+- *
+- * @hdr: Generic Header
+- * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
+- * @index: ring index.
+- */
+-struct ti_sci_msg_rm_ring_get_cfg_req {
+-	struct ti_sci_msg_hdr hdr;
+-	u16 nav_id;
+-	u16 index;
+-} __packed;
+-
+-/**
+- * struct ti_sci_msg_rm_ring_get_cfg_resp -  Ring get configuration response
+- *
+- * Response received by host processor after RM has handled
+- * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
+- * non-real-time register values.
+- *
+- * @hdr: Generic Header
+- * @addr_lo: Ring 32 LSBs of base address
+- * @addr_hi: Ring 16 MSBs of base address.
+- * @count: Ring number of elements.
+- * @mode: Ring mode.
+- * @size: encoded Ring element size
+- * @order_id: ing order ID.
+- */
+-struct ti_sci_msg_rm_ring_get_cfg_resp {
+-	struct ti_sci_msg_hdr hdr;
+-	u32 addr_lo;
+-	u32 addr_hi;
+-	u32 count;
+-	u8 mode;
+-	u8 size;
+-	u8 order_id;
+-} __packed;
+-
+ /**
+  * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
+  *				 thread
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index a090b72a3362..7727ec954f62 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -286,8 +286,6 @@ struct ti_sci_rm_irq_ops {
+ /**
+  * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
+  * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
+- * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
+- *		configuration
+  */
+ struct ti_sci_rm_ringacc_ops {
+ 	int (*config)(const struct ti_sci_handle *handle,
+@@ -295,10 +293,6 @@ struct ti_sci_rm_ringacc_ops {
+ 		      u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
+ 		      u8 size, u8 order_id
+ 	);
+-	int (*get_config)(const struct ti_sci_handle *handle,
+-			  u32 nav_id, u32 index, u8 *mode,
+-			  u32 *addr_lo, u32 *addr_hi, u32 *count,
+-			  u8 *size, u8 *order_id);
+ };
+ 
+ /**

board/PSG/iot2050/files/patches-5.10/0025-firmware-ti_sci-rm-Add-new-ops-for-ring-configuratio.patch

@@ -0,0 +1,198 @@
+From db5dded64c9de553bed288acc9cacc8d49b5ea97 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:06 -0700
+Subject: [PATCH] firmware: ti_sci: rm: Add new ops for ring configuration
+
+The sysfw ring configuration message has been extended to include virtid
+and asel value for the ring.
+Add the ASEL_VALID to TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER as it is required
+for DMA rings.
+
+Instead of extending the current .config() ops - which would need same
+patch change in the ringacc driver - add ti_sci_msg_rm_ring_cfg struct and
+a new ops using it to configure the ring.
+
+This will allow easy update path in case new members are added for the ring
+configuration.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 63 ++++++++++++++++++++++++++
+ drivers/firmware/ti_sci.h              |  7 +++
+ include/linux/soc/ti/ti_sci_protocol.h | 31 ++++++++++++-
+ 3 files changed, 100 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index 0b801e67e672..a4d2b318795c 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -2119,6 +2119,68 @@ static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
+ 	return ret;
+ }
+ 
++/**
++ * ti_sci_cmd_rm_ring_cfg() - Configure a NAVSS ring
++ * @handle:	Pointer to TI SCI handle.
++ * @params:	Pointer to ti_sci_msg_rm_ring_cfg ring config structure
++ *
++ * Return: 0 if all went well, else returns appropriate error value.
++ *
++ * See @ti_sci_msg_rm_ring_cfg and @ti_sci_msg_rm_ring_cfg_req for
++ * more info.
++ */
++static int ti_sci_cmd_rm_ring_cfg(const struct ti_sci_handle *handle,
++				  const struct ti_sci_msg_rm_ring_cfg *params)
++{
++	struct ti_sci_msg_rm_ring_cfg_req *req;
++	struct ti_sci_msg_hdr *resp;
++	struct ti_sci_xfer *xfer;
++	struct ti_sci_info *info;
++	struct device *dev;
++	int ret = 0;
++
++	if (IS_ERR_OR_NULL(handle))
++		return -EINVAL;
++
++	info = handle_to_ti_sci_info(handle);
++	dev = info->dev;
++
++	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_CFG,
++				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
++				   sizeof(*req), sizeof(*resp));
++	if (IS_ERR(xfer)) {
++		ret = PTR_ERR(xfer);
++		dev_err(dev, "RM_RA:Message config failed(%d)\n", ret);
++		return ret;
++	}
++	req = (struct ti_sci_msg_rm_ring_cfg_req *)xfer->xfer_buf;
++	req->valid_params = params->valid_params;
++	req->nav_id = params->nav_id;
++	req->index = params->index;
++	req->addr_lo = params->addr_lo;
++	req->addr_hi = params->addr_hi;
++	req->count = params->count;
++	req->mode = params->mode;
++	req->size = params->size;
++	req->order_id = params->order_id;
++	req->virtid = params->virtid;
++	req->asel = params->asel;
++
++	ret = ti_sci_do_xfer(info, xfer);
++	if (ret) {
++		dev_err(dev, "RM_RA:Mbox config send fail %d\n", ret);
++		goto fail;
++	}
++
++	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;
++	ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL;
++
++fail:
++	ti_sci_put_one_xfer(&info->minfo, xfer);
++	dev_dbg(dev, "RM_RA:config ring %u ret:%d\n", params->index, ret);
++	return ret;
++}
++
+ /**
+  * ti_sci_cmd_rm_psil_pair() - Pair PSI-L source to destination thread
+  * @handle:	Pointer to TI SCI handle.
+@@ -2847,6 +2909,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
+ 	iops->free_event_map = ti_sci_cmd_free_event_map;
+ 
+ 	rops->config = ti_sci_cmd_ring_config;
++	rops->set_cfg = ti_sci_cmd_rm_ring_cfg;
+ 
+ 	psilops->pair = ti_sci_cmd_rm_psil_pair;
+ 	psilops->unpair = ti_sci_cmd_rm_psil_unpair;
+diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
+index 1cdf918be861..ef3a8214d002 100644
+--- a/drivers/firmware/ti_sci.h
++++ b/drivers/firmware/ti_sci.h
+@@ -659,6 +659,8 @@ struct ti_sci_msg_req_manage_irq {
+  *	3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
+  *	4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
+  *	5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
++ *	6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
++ *	7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
+  * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
+  * @index: ring index to be configured.
+  * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
+@@ -672,6 +674,9 @@ struct ti_sci_msg_req_manage_irq {
+  *	the formula (log2(size_bytes) - 2), where size_bytes cannot be
+  *	greater than 256.
+  * @order_id: Specifies the ring's bus order ID.
++ * @virtid: Ring virt ID value
++ * @asel: Ring ASEL (address select) value to be set into the ASEL field of the
++ *	ring's RING_BA_HI register.
+  */
+ struct ti_sci_msg_rm_ring_cfg_req {
+ 	struct ti_sci_msg_hdr hdr;
+@@ -684,6 +689,8 @@ struct ti_sci_msg_rm_ring_cfg_req {
+ 	u8 mode;
+ 	u8 size;
+ 	u8 order_id;
++	u16 virtid;
++	u8 asel;
+ } __packed;
+ 
+ /**
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index 7727ec954f62..d7f0dcf98861 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -275,17 +275,44 @@ struct ti_sci_rm_irq_ops {
+ #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID	BIT(4)
+ /* RA config.order_id parameter is valid for RM ring configure TISCI message */
+ #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID	BIT(5)
++/* RA config.virtid parameter is valid for RM ring configure TISCI message */
++#define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID	BIT(6)
++/* RA config.asel parameter is valid for RM ring configure TISCI message */
++#define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID	BIT(7)
+ 
+ #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
+ 	(TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
+ 	TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
+ 	TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
+ 	TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
+-	TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
++	TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \
++	TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID)
++
++/**
++ * struct ti_sci_msg_rm_ring_cfg - Ring configuration
++ *
++ * Parameters for Navigator Subsystem ring configuration
++ * See @ti_sci_msg_rm_ring_cfg_req
++ */
++struct ti_sci_msg_rm_ring_cfg {
++	u32 valid_params;
++	u16 nav_id;
++	u16 index;
++	u32 addr_lo;
++	u32 addr_hi;
++	u32 count;
++	u8 mode;
++	u8 size;
++	u8 order_id;
++	u16 virtid;
++	u8 asel;
++};
+ 
+ /**
+  * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
+  * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
++ *	    Deprecated
++ * @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
+  */
+ struct ti_sci_rm_ringacc_ops {
+ 	int (*config)(const struct ti_sci_handle *handle,
+@@ -293,6 +320,8 @@ struct ti_sci_rm_ringacc_ops {
+ 		      u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
+ 		      u8 size, u8 order_id
+ 	);
++	int (*set_cfg)(const struct ti_sci_handle *handle,
++		       const struct ti_sci_msg_rm_ring_cfg *params);
+ };
+ 
+ /**

board/PSG/iot2050/files/patches-5.10/0026-soc-ti-k3-ringacc-Use-the-ti_sci-set_cfg-callback-fo.patch

@@ -0,0 +1,143 @@
+From 8c78f49472021ef132d44f72bbf0548885d740b6 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:07 -0700
+Subject: [PATCH] soc: ti: k3-ringacc: Use the ti_sci set_cfg callback for ring
+ configuration
+
+Switch to the new set_cfg to configure the ring.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/k3-ringacc.c | 79 +++++++++++++++----------------------
+ 1 file changed, 32 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c
+index 1147dc4c1d59..9ddd77113c5a 100644
+--- a/drivers/soc/ti/k3-ringacc.c
++++ b/drivers/soc/ti/k3-ringacc.c
+@@ -365,20 +365,16 @@ EXPORT_SYMBOL_GPL(k3_ringacc_request_rings_pair);
+ 
+ static void k3_ringacc_ring_reset_sci(struct k3_ring *ring)
+ {
++	struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
+ 	struct k3_ringacc *ringacc = ring->parent;
+ 	int ret;
+ 
+-	ret = ringacc->tisci_ring_ops->config(
+-			ringacc->tisci,
+-			TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
+-			ringacc->tisci_dev_id,
+-			ring->ring_id,
+-			0,
+-			0,
+-			ring->size,
+-			0,
+-			0,
+-			0);
++	ring_cfg.nav_id = ringacc->tisci_dev_id;
++	ring_cfg.index = ring->ring_id;
++	ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID;
++	ring_cfg.count = ring->size;
++
++	ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ 	if (ret)
+ 		dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n",
+ 			ret, ring->ring_id);
+@@ -398,20 +394,16 @@ EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset);
+ static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring,
+ 					       enum k3_ring_mode mode)
+ {
++	struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
+ 	struct k3_ringacc *ringacc = ring->parent;
+ 	int ret;
+ 
+-	ret = ringacc->tisci_ring_ops->config(
+-			ringacc->tisci,
+-			TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
+-			ringacc->tisci_dev_id,
+-			ring->ring_id,
+-			0,
+-			0,
+-			0,
+-			mode,
+-			0,
+-			0);
++	ring_cfg.nav_id = ringacc->tisci_dev_id;
++	ring_cfg.index = ring->ring_id;
++	ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID;
++	ring_cfg.mode = mode;
++
++	ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ 	if (ret)
+ 		dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n",
+ 			ret, ring->ring_id);
+@@ -478,20 +470,15 @@ EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset_dma);
+ 
+ static void k3_ringacc_ring_free_sci(struct k3_ring *ring)
+ {
++	struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
+ 	struct k3_ringacc *ringacc = ring->parent;
+ 	int ret;
+ 
+-	ret = ringacc->tisci_ring_ops->config(
+-			ringacc->tisci,
+-			TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
+-			ringacc->tisci_dev_id,
+-			ring->ring_id,
+-			0,
+-			0,
+-			0,
+-			0,
+-			0,
+-			0);
++	ring_cfg.nav_id = ringacc->tisci_dev_id;
++	ring_cfg.index = ring->ring_id;
++	ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
++
++	ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ 	if (ret)
+ 		dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n",
+ 			ret, ring->ring_id);
+@@ -575,28 +562,26 @@ EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num);
+ 
+ static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring)
+ {
++	struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 };
+ 	struct k3_ringacc *ringacc = ring->parent;
+-	u32 ring_idx;
+ 	int ret;
+ 
+ 	if (!ringacc->tisci)
+ 		return -EINVAL;
+ 
+-	ring_idx = ring->ring_id;
+-	ret = ringacc->tisci_ring_ops->config(
+-			ringacc->tisci,
+-			TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
+-			ringacc->tisci_dev_id,
+-			ring_idx,
+-			lower_32_bits(ring->ring_mem_dma),
+-			upper_32_bits(ring->ring_mem_dma),
+-			ring->size,
+-			ring->mode,
+-			ring->elm_size,
+-			0);
++	ring_cfg.nav_id = ringacc->tisci_dev_id;
++	ring_cfg.index = ring->ring_id;
++	ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER;
++	ring_cfg.addr_lo = lower_32_bits(ring->ring_mem_dma);
++	ring_cfg.addr_hi = upper_32_bits(ring->ring_mem_dma);
++	ring_cfg.count = ring->size;
++	ring_cfg.mode = ring->mode;
++	ring_cfg.size = ring->elm_size;
++
++	ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg);
+ 	if (ret)
+ 		dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
+-			ret, ring_idx);
++			ret, ring->ring_id);
+ 
+ 	return ret;
+ }

board/PSG/iot2050/files/patches-5.10/0027-firmware-ti_sci-rm-Remove-unused-config-from-ti_sci_.patch

@@ -0,0 +1,128 @@
+From 7c4be2c85412c69aded0dd19b7bd1073cd48cd06 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:07 -0700
+Subject: [PATCH] firmware: ti_sci: rm: Remove unused config() from
+ ti_sci_rm_ringacc_ops
+
+The ringacc driver has been converted to use the new set_cfg function to
+configure the ring, the old config ops can be removed.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/firmware/ti_sci.c              | 72 --------------------------
+ include/linux/soc/ti/ti_sci_protocol.h |  7 ---
+ 2 files changed, 79 deletions(-)
+
+diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
+index a4d2b318795c..235c7e7869aa 100644
+--- a/drivers/firmware/ti_sci.c
++++ b/drivers/firmware/ti_sci.c
+@@ -2048,77 +2048,6 @@ static int ti_sci_cmd_free_event_map(const struct ti_sci_handle *handle,
+ 			       ia_id, vint, global_event, vint_status_bit, 0);
+ }
+ 
+-/**
+- * ti_sci_cmd_ring_config() - configure RA ring
+- * @handle:		Pointer to TI SCI handle.
+- * @valid_params:	Bitfield defining validity of ring configuration
+- *			parameters
+- * @nav_id:		Device ID of Navigator Subsystem from which the ring is
+- *			allocated
+- * @index:		Ring index
+- * @addr_lo:		The ring base address lo 32 bits
+- * @addr_hi:		The ring base address hi 32 bits
+- * @count:		Number of ring elements
+- * @mode:		The mode of the ring
+- * @size:		The ring element size.
+- * @order_id:		Specifies the ring's bus order ID
+- *
+- * Return: 0 if all went well, else returns appropriate error value.
+- *
+- * See @ti_sci_msg_rm_ring_cfg_req for more info.
+- */
+-static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle,
+-				  u32 valid_params, u16 nav_id, u16 index,
+-				  u32 addr_lo, u32 addr_hi, u32 count,
+-				  u8 mode, u8 size, u8 order_id)
+-{
+-	struct ti_sci_msg_rm_ring_cfg_req *req;
+-	struct ti_sci_msg_hdr *resp;
+-	struct ti_sci_xfer *xfer;
+-	struct ti_sci_info *info;
+-	struct device *dev;
+-	int ret = 0;
+-
+-	if (IS_ERR_OR_NULL(handle))
+-		return -EINVAL;
+-
+-	info = handle_to_ti_sci_info(handle);
+-	dev = info->dev;
+-
+-	xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_CFG,
+-				   TI_SCI_FLAG_REQ_ACK_ON_PROCESSED,
+-				   sizeof(*req), sizeof(*resp));
+-	if (IS_ERR(xfer)) {
+-		ret = PTR_ERR(xfer);
+-		dev_err(dev, "RM_RA:Message config failed(%d)\n", ret);
+-		return ret;
+-	}
+-	req = (struct ti_sci_msg_rm_ring_cfg_req *)xfer->xfer_buf;
+-	req->valid_params = valid_params;
+-	req->nav_id = nav_id;
+-	req->index = index;
+-	req->addr_lo = addr_lo;
+-	req->addr_hi = addr_hi;
+-	req->count = count;
+-	req->mode = mode;
+-	req->size = size;
+-	req->order_id = order_id;
+-
+-	ret = ti_sci_do_xfer(info, xfer);
+-	if (ret) {
+-		dev_err(dev, "RM_RA:Mbox config send fail %d\n", ret);
+-		goto fail;
+-	}
+-
+-	resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf;
+-	ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV;
+-
+-fail:
+-	ti_sci_put_one_xfer(&info->minfo, xfer);
+-	dev_dbg(dev, "RM_RA:config ring %u ret:%d\n", index, ret);
+-	return ret;
+-}
+-
+ /**
+  * ti_sci_cmd_rm_ring_cfg() - Configure a NAVSS ring
+  * @handle:	Pointer to TI SCI handle.
+@@ -2908,7 +2837,6 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
+ 	iops->free_irq = ti_sci_cmd_free_irq;
+ 	iops->free_event_map = ti_sci_cmd_free_event_map;
+ 
+-	rops->config = ti_sci_cmd_ring_config;
+ 	rops->set_cfg = ti_sci_cmd_rm_ring_cfg;
+ 
+ 	psilops->pair = ti_sci_cmd_rm_psil_pair;
+diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
+index d7f0dcf98861..bd0d11af76c5 100644
+--- a/include/linux/soc/ti/ti_sci_protocol.h
++++ b/include/linux/soc/ti/ti_sci_protocol.h
+@@ -310,16 +310,9 @@ struct ti_sci_msg_rm_ring_cfg {
+ 
+ /**
+  * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
+- * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
+- *	    Deprecated
+  * @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring
+  */
+ struct ti_sci_rm_ringacc_ops {
+-	int (*config)(const struct ti_sci_handle *handle,
+-		      u32 valid_params, u16 nav_id, u16 index,
+-		      u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
+-		      u8 size, u8 order_id
+-	);
+ 	int (*set_cfg)(const struct ti_sci_handle *handle,
+ 		       const struct ti_sci_msg_rm_ring_cfg *params);
+ };

board/PSG/iot2050/files/patches-5.10/0028-soc-ti-k3-ringacc-Use-correct-device-for-allocation-.patch

@@ -0,0 +1,127 @@
+From efa19303e35f82243a781df500c6e0f93aabb489 Mon Sep 17 00:00:00 2001
+From: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Date: Sun, 25 Oct 2020 12:10:22 -0700
+Subject: [PATCH] soc: ti: k3-ringacc: Use correct device for allocation in
+ RING mode
+
+In RING mode the ringacc does not access the ring memory. In this access
+mode the ringacc coherency does not have meaning.
+
+If the ring is configured in RING mode, then the ringacc itself will not
+access to the ring memory. Only the requester (user) of the ring is going
+to read/write to the memory.
+Extend the ring configuration parameters with a device pointer to be used
+for DMA API when the ring is configured in RING mode.
+
+Extending the ring configuration struct will allow per ring selection of
+device to be used for allocation, thus allowing per ring coherency.
+
+To avoid regression, fall back to use the ringacc dev in case the alloc_dev
+is not provided.
+
+Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
+Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/k3-ringacc.c       | 18 +++++++++++++-----
+ include/linux/soc/ti/k3-ringacc.h |  5 +++++
+ 2 files changed, 18 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c
+index 9ddd77113c5a..7fdb688452f7 100644
+--- a/drivers/soc/ti/k3-ringacc.c
++++ b/drivers/soc/ti/k3-ringacc.c
+@@ -141,6 +141,7 @@ struct k3_ring_state {
+  * @parent: Pointer on struct @k3_ringacc
+  * @use_count: Use count for shared rings
+  * @proxy_id: RA Ring Proxy Id (only if @K3_RINGACC_RING_USE_PROXY)
++ * @dma_dev: device to be used for DMA API (allocation, mapping)
+  */
+ struct k3_ring {
+ 	struct k3_ring_rt_regs __iomem *rt;
+@@ -160,6 +161,7 @@ struct k3_ring {
+ 	struct k3_ringacc	*parent;
+ 	u32		use_count;
+ 	int		proxy_id;
++	struct device	*dma_dev;
+ };
+ 
+ struct k3_ringacc_ops {
+@@ -508,11 +510,12 @@ int k3_ringacc_ring_free(struct k3_ring *ring)
+ 
+ 	k3_ringacc_ring_free_sci(ring);
+ 
+-	dma_free_coherent(ringacc->dev,
++	dma_free_coherent(ring->dma_dev,
+ 			  ring->size * (4 << ring->elm_size),
+ 			  ring->ring_mem_virt, ring->ring_mem_dma);
+ 	ring->flags = 0;
+ 	ring->ops = NULL;
++	ring->dma_dev = NULL;
+ 	if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) {
+ 		clear_bit(ring->proxy_id, ringacc->proxy_inuse);
+ 		ring->proxy = NULL;
+@@ -633,8 +636,12 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
+ 	switch (ring->mode) {
+ 	case K3_RINGACC_RING_MODE_RING:
+ 		ring->ops = &k3_ring_mode_ring_ops;
++		ring->dma_dev = cfg->dma_dev;
++		if (!ring->dma_dev)
++			ring->dma_dev = ringacc->dev;
+ 		break;
+ 	case K3_RINGACC_RING_MODE_MESSAGE:
++		ring->dma_dev = ringacc->dev;
+ 		if (ring->proxy)
+ 			ring->ops = &k3_ring_mode_proxy_ops;
+ 		else
+@@ -646,9 +653,9 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
+ 		goto err_free_proxy;
+ 	}
+ 
+-	ring->ring_mem_virt = dma_alloc_coherent(ringacc->dev,
+-					ring->size * (4 << ring->elm_size),
+-					&ring->ring_mem_dma, GFP_KERNEL);
++	ring->ring_mem_virt = dma_alloc_coherent(ring->dma_dev,
++						 ring->size * (4 << ring->elm_size),
++						 &ring->ring_mem_dma, GFP_KERNEL);
+ 	if (!ring->ring_mem_virt) {
+ 		dev_err(ringacc->dev, "Failed to alloc ring mem\n");
+ 		ret = -ENOMEM;
+@@ -669,12 +676,13 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg)
+ 	return 0;
+ 
+ err_free_mem:
+-	dma_free_coherent(ringacc->dev,
++	dma_free_coherent(ring->dma_dev,
+ 			  ring->size * (4 << ring->elm_size),
+ 			  ring->ring_mem_virt,
+ 			  ring->ring_mem_dma);
+ err_free_ops:
+ 	ring->ops = NULL;
++	ring->dma_dev = NULL;
+ err_free_proxy:
+ 	ring->proxy = NULL;
+ 	return ret;
+diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h
+index 5a472eca5ee4..658dc71d2901 100644
+--- a/include/linux/soc/ti/k3-ringacc.h
++++ b/include/linux/soc/ti/k3-ringacc.h
+@@ -67,6 +67,9 @@ struct k3_ring;
+  *	 few times. It's usable when the same ring is used as Free Host PD ring
+  *	 for different flows, for example.
+  *	 Note: Locking should be done by consumer if required
++ * @dma_dev: Master device which is using and accessing to the ring
++ *	memory when the mode is K3_RINGACC_RING_MODE_RING. Memory allocations
++ *	should be done using this device.
+  */
+ struct k3_ring_cfg {
+ 	u32 size;
+@@ -74,6 +77,8 @@ struct k3_ring_cfg {
+ 	enum k3_ring_mode mode;
+ #define K3_RINGACC_RING_SHARED BIT(1)
+ 	u32 flags;
++
++	struct device *dma_dev;
+ };
+ 
+ #define K3_RINGACC_RING_ID_ANY (-1)

board/PSG/iot2050/files/patches-5.10/0029-soc-ti-pruss-Remove-wrong-check-against-get_match_da.patch

@@ -0,0 +1,44 @@
+From a0398928ea759d68975836acf8c8888af6497341 Mon Sep 17 00:00:00 2001
+From: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Date: Sat, 21 Nov 2020 19:22:25 -0800
+Subject: [PATCH] soc: ti: pruss: Remove wrong check against *get_match_data
+ return value
+
+Since the of_device_get_match_data() doesn't return error code, remove
+wrong IS_ERR test. Proper check against NULL pointer is already done
+later before usage: if (data && data->...).
+
+Additionally, proceeding with empty device data is valid (e.g. in case
+of "ti,am3356-pruss").
+
+Reported-by: Wei Yongjun <weiyongjun1@huawei.com>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/pruss.c | 6 ------
+ 1 file changed, 6 deletions(-)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index 30695172a508..aa3aba80dbc6 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -126,8 +126,6 @@ static int pruss_clk_init(struct pruss *pruss, struct device_node *cfg_node)
+ 	int ret = 0;
+ 
+ 	data = of_device_get_match_data(dev);
+-	if (IS_ERR(data))
+-		return -ENODEV;
+ 
+ 	clks_np = of_get_child_by_name(cfg_node, "clocks");
+ 	if (!clks_np) {
+@@ -175,10 +173,6 @@ static int pruss_probe(struct platform_device *pdev)
+ 	const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" };
+ 
+ 	data = of_device_get_match_data(&pdev->dev);
+-	if (IS_ERR(data)) {
+-		dev_err(dev, "missing private data\n");
+-		return -ENODEV;
+-	}
+ 
+ 	ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+ 	if (ret) {

board/PSG/iot2050/files/patches-5.10/0030-soc-ti-pruss-Correct-the-pruss_clk_init-error-trace-.patch

@@ -0,0 +1,28 @@
+From eb15c044dcb42f89a094bf02ccced2b1e54535e5 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Sun, 24 Jan 2021 20:51:37 -0800
+Subject: [PATCH] soc: ti: pruss: Correct the pruss_clk_init error trace text
+
+The pruss_clk_init() function can register more than one clock.
+Correct the existing misleading error trace upon a failure within
+this function.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/pruss.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index aa3aba80dbc6..dc94335fc351 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -273,7 +273,7 @@ static int pruss_probe(struct platform_device *pdev)
+ 
+ 	ret = pruss_clk_init(pruss, child);
+ 	if (ret) {
+-		dev_err(dev, "failed to setup coreclk-mux\n");
++		dev_err(dev, "pruss_clk_init failed, ret = %d\n", ret);
+ 		goto node_put;
+ 	}
+ 

board/PSG/iot2050/files/patches-5.10/0031-soc-ti-pruss-Refactor-the-CFG-sub-module-init.patch

@@ -0,0 +1,135 @@
+From 0b81c5fbe821f75cf21be29afb9952a47ac40a50 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Sun, 31 Jan 2021 20:53:43 -0800
+Subject: [PATCH] soc: ti: pruss: Refactor the CFG sub-module init
+
+The CFG sub-module is not present on some earlier SoCs like the
+DA850/OMAPL-138 in the TI Davinci family. Refactor out the CFG
+sub-module parse and initialization logic into a separate function
+to make it easier to add logic for the PRUSS IP on the above legacy
+SoC families.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/pruss.c | 91 +++++++++++++++++++++++-------------------
+ 1 file changed, 50 insertions(+), 41 deletions(-)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index dc94335fc351..afc8aae68035 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -161,6 +161,53 @@ static struct regmap_config regmap_conf = {
+ 	.reg_stride = 4,
+ };
+ 
++static int pruss_cfg_of_init(struct device *dev, struct pruss *pruss)
++{
++	struct device_node *np = dev_of_node(dev);
++	struct device_node *child;
++	struct resource res;
++	int ret;
++
++	child = of_get_child_by_name(np, "cfg");
++	if (!child) {
++		dev_err(dev, "%pOF is missing its 'cfg' node\n", child);
++		return -ENODEV;
++	}
++
++	if (of_address_to_resource(child, 0, &res)) {
++		ret = -ENOMEM;
++		goto node_put;
++	}
++
++	pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res));
++	if (!pruss->cfg_base) {
++		ret = -ENOMEM;
++		goto node_put;
++	}
++
++	regmap_conf.name = kasprintf(GFP_KERNEL, "%pOFn@%llx", child,
++				     (u64)res.start);
++	regmap_conf.max_register = resource_size(&res) - 4;
++
++	pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base,
++						  &regmap_conf);
++	kfree(regmap_conf.name);
++	if (IS_ERR(pruss->cfg_regmap)) {
++		dev_err(dev, "regmap_init_mmio failed for cfg, ret = %ld\n",
++			PTR_ERR(pruss->cfg_regmap));
++		ret = PTR_ERR(pruss->cfg_regmap);
++		goto node_put;
++	}
++
++	ret = pruss_clk_init(pruss, child);
++	if (ret)
++		dev_err(dev, "pruss_clk_init failed, ret = %d\n", ret);
++
++node_put:
++	of_node_put(child);
++	return ret;
++}
++
+ static int pruss_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -239,56 +286,18 @@ static int pruss_probe(struct platform_device *pdev)
+ 		goto rpm_disable;
+ 	}
+ 
+-	child = of_get_child_by_name(np, "cfg");
+-	if (!child) {
+-		dev_err(dev, "%pOF is missing its 'cfg' node\n", child);
+-		ret = -ENODEV;
++	ret = pruss_cfg_of_init(dev, pruss);
++	if (ret < 0)
+ 		goto rpm_put;
+-	}
+-
+-	if (of_address_to_resource(child, 0, &res)) {
+-		ret = -ENOMEM;
+-		goto node_put;
+-	}
+-
+-	pruss->cfg_base = devm_ioremap(dev, res.start, resource_size(&res));
+-	if (!pruss->cfg_base) {
+-		ret = -ENOMEM;
+-		goto node_put;
+-	}
+-
+-	regmap_conf.name = kasprintf(GFP_KERNEL, "%pOFn@%llx", child,
+-				     (u64)res.start);
+-	regmap_conf.max_register = resource_size(&res) - 4;
+-
+-	pruss->cfg_regmap = devm_regmap_init_mmio(dev, pruss->cfg_base,
+-						  &regmap_conf);
+-	kfree(regmap_conf.name);
+-	if (IS_ERR(pruss->cfg_regmap)) {
+-		dev_err(dev, "regmap_init_mmio failed for cfg, ret = %ld\n",
+-			PTR_ERR(pruss->cfg_regmap));
+-		ret = PTR_ERR(pruss->cfg_regmap);
+-		goto node_put;
+-	}
+-
+-	ret = pruss_clk_init(pruss, child);
+-	if (ret) {
+-		dev_err(dev, "pruss_clk_init failed, ret = %d\n", ret);
+-		goto node_put;
+-	}
+ 
+ 	ret = devm_of_platform_populate(dev);
+ 	if (ret) {
+ 		dev_err(dev, "failed to register child devices\n");
+-		goto node_put;
++		goto rpm_put;
+ 	}
+ 
+-	of_node_put(child);
+-
+ 	return 0;
+ 
+-node_put:
+-	of_node_put(child);
+ rpm_put:
+ 	pm_runtime_put_sync(dev);
+ rpm_disable:

board/PSG/iot2050/files/patches-5.10/0032-soc-ti-k3-ringacc-Use-of_device_get_match_data.patch

@@ -0,0 +1,45 @@
+From 04cc43da37c9edee528e1ecd1af57deaa9b33b68 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Sun, 31 Jan 2021 20:58:49 -0800
+Subject: [PATCH] soc: ti: k3-ringacc: Use of_device_get_match_data()
+
+Simplify the retrieval of getting the match data in the probe
+function by directly using of_device_get_match_data() instead
+of using of_match_node() and getting data.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
+---
+ drivers/soc/ti/k3-ringacc.c | 7 +++----
+ 1 file changed, 3 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c
+index 7fdb688452f7..db3f705da7a0 100644
+--- a/drivers/soc/ti/k3-ringacc.c
++++ b/drivers/soc/ti/k3-ringacc.c
+@@ -9,6 +9,7 @@
+ #include <linux/io.h>
+ #include <linux/init.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/sys_soc.h>
+ #include <linux/soc/ti/k3-ringacc.h>
+@@ -1205,15 +1206,13 @@ static const struct of_device_id k3_ringacc_of_match[] = {
+ static int k3_ringacc_probe(struct platform_device *pdev)
+ {
+ 	const struct ringacc_match_data *match_data;
+-	const struct of_device_id *match;
+ 	struct device *dev = &pdev->dev;
+ 	struct k3_ringacc *ringacc;
+ 	int ret;
+ 
+-	match = of_match_node(k3_ringacc_of_match, dev->of_node);
+-	if (!match)
++	match_data = of_device_get_match_data(&pdev->dev);
++	if (!match_data)
+ 		return -ENODEV;
+-	match_data = match->data;
+ 
+ 	ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
+ 	if (!ringacc)

board/PSG/iot2050/files/patches-5.10/0033-remoteproc-ti_k3-fix-Wcast-function-type-warning.patch

@@ -0,0 +1,80 @@
+From 05fa83d5672bc9469f05f678ddca541982d202d7 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Mon, 26 Oct 2020 17:05:23 +0100
+Subject: [PATCH] remoteproc: ti_k3: fix -Wcast-function-type warning
+
+The function cast causes a warning with "make W=1"
+
+drivers/remoteproc/ti_k3_r5_remoteproc.c: In function 'k3_r5_probe':
+drivers/remoteproc/ti_k3_r5_remoteproc.c:1368:12: warning: cast between incompatible function types from 'int (*)(struct platform_device *)' to 'void (*)(void *)' [-Wcast-function-type]
+
+Rewrite the code to avoid the cast, and fix the incorrect return
+type of the callback.
+
+Fixes: 6dedbd1d5443 ("remoteproc: k3-r5: Add a remoteproc driver for R5F subsystem")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Link: https://lore.kernel.org/r/20201026160533.3705998-1-arnd@kernel.org
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/ti_k3_r5_remoteproc.c | 18 ++++++------------
+ 1 file changed, 6 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/remoteproc/ti_k3_r5_remoteproc.c b/drivers/remoteproc/ti_k3_r5_remoteproc.c
+index f92a18c06d80..e5346251db0f 100644
+--- a/drivers/remoteproc/ti_k3_r5_remoteproc.c
++++ b/drivers/remoteproc/ti_k3_r5_remoteproc.c
+@@ -940,9 +940,9 @@ static int k3_r5_cluster_rproc_init(struct platform_device *pdev)
+ 	return ret;
+ }
+ 
+-static int k3_r5_cluster_rproc_exit(struct platform_device *pdev)
++static void k3_r5_cluster_rproc_exit(void *data)
+ {
+-	struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
++	struct k3_r5_cluster *cluster = platform_get_drvdata(data);
+ 	struct k3_r5_rproc *kproc;
+ 	struct k3_r5_core *core;
+ 	struct rproc *rproc;
+@@ -967,8 +967,6 @@ static int k3_r5_cluster_rproc_exit(struct platform_device *pdev)
+ 		rproc_free(rproc);
+ 		core->rproc = NULL;
+ 	}
+-
+-	return 0;
+ }
+ 
+ static int k3_r5_core_of_get_internal_memories(struct platform_device *pdev,
+@@ -1255,9 +1253,9 @@ static void k3_r5_core_of_exit(struct platform_device *pdev)
+ 	devres_release_group(dev, k3_r5_core_of_init);
+ }
+ 
+-static void k3_r5_cluster_of_exit(struct platform_device *pdev)
++static void k3_r5_cluster_of_exit(void *data)
+ {
+-	struct k3_r5_cluster *cluster = platform_get_drvdata(pdev);
++	struct k3_r5_cluster *cluster = platform_get_drvdata(data);
+ 	struct platform_device *cpdev;
+ 	struct k3_r5_core *core, *temp;
+ 
+@@ -1353,9 +1351,7 @@ static int k3_r5_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	ret = devm_add_action_or_reset(dev,
+-				       (void(*)(void *))k3_r5_cluster_of_exit,
+-				       pdev);
++	ret = devm_add_action_or_reset(dev, k3_r5_cluster_of_exit, pdev);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -1366,9 +1362,7 @@ static int k3_r5_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	ret = devm_add_action_or_reset(dev,
+-				       (void(*)(void *))k3_r5_cluster_rproc_exit,
+-				       pdev);
++	ret = devm_add_action_or_reset(dev, k3_r5_cluster_rproc_exit, pdev);
+ 	if (ret)
+ 		return ret;
+ 

board/PSG/iot2050/files/patches-5.10/0034-remoteproc-Add-a-rproc_set_firmware-API.patch

@@ -0,0 +1,160 @@
+From dad5882905f5a36cb65d2b4193ca08a159b53bea Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 20 Nov 2020 21:20:42 -0600
+Subject: [PATCH] remoteproc: Add a rproc_set_firmware() API
+
+A new API, rproc_set_firmware() is added to allow the remoteproc platform
+drivers and remoteproc client drivers to be able to configure a custom
+firmware name that is different from the default name used during
+remoteproc registration. This function is being introduced to provide
+a kernel-level equivalent of the current sysfs interface to remoteproc
+client drivers, and can only change firmwares when the remoteproc is
+offline. This allows some remoteproc drivers to choose different firmwares
+at runtime based on the functionality the remote processor is providing.
+The TI PRU Ethernet driver will be an example of such usage as it
+requires to use different firmwares for different supported protocols.
+
+Also, update the firmware_store() function used by the sysfs interface
+to reuse this function to avoid code duplication.
+
+Reviewed-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Link: https://lore.kernel.org/r/20201121032042.6195-1-s-anna@ti.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/remoteproc_core.c  | 63 +++++++++++++++++++++++++++
+ drivers/remoteproc/remoteproc_sysfs.c | 33 +-------------
+ include/linux/remoteproc.h            |  1 +
+ 3 files changed, 66 insertions(+), 31 deletions(-)
+
+diff --git a/drivers/remoteproc/remoteproc_core.c b/drivers/remoteproc/remoteproc_core.c
+index 369a97f3eca9..5250a081ea93 100644
+--- a/drivers/remoteproc/remoteproc_core.c
++++ b/drivers/remoteproc/remoteproc_core.c
+@@ -1936,6 +1936,69 @@ struct rproc *rproc_get_by_phandle(phandle phandle)
+ #endif
+ EXPORT_SYMBOL(rproc_get_by_phandle);
+ 
++/**
++ * rproc_set_firmware() - assign a new firmware
++ * @rproc: rproc handle to which the new firmware is being assigned
++ * @fw_name: new firmware name to be assigned
++ *
++ * This function allows remoteproc drivers or clients to configure a custom
++ * firmware name that is different from the default name used during remoteproc
++ * registration. The function does not trigger a remote processor boot,
++ * only sets the firmware name used for a subsequent boot. This function
++ * should also be called only when the remote processor is offline.
++ *
++ * This allows either the userspace to configure a different name through
++ * sysfs or a kernel-level remoteproc or a remoteproc client driver to set
++ * a specific firmware when it is controlling the boot and shutdown of the
++ * remote processor.
++ *
++ * Return: 0 on success or a negative value upon failure
++ */
++int rproc_set_firmware(struct rproc *rproc, const char *fw_name)
++{
++	struct device *dev;
++	int ret, len;
++	char *p;
++
++	if (!rproc || !fw_name)
++		return -EINVAL;
++
++	dev = rproc->dev.parent;
++
++	ret = mutex_lock_interruptible(&rproc->lock);
++	if (ret) {
++		dev_err(dev, "can't lock rproc %s: %d\n", rproc->name, ret);
++		return -EINVAL;
++	}
++
++	if (rproc->state != RPROC_OFFLINE) {
++		dev_err(dev, "can't change firmware while running\n");
++		ret = -EBUSY;
++		goto out;
++	}
++
++	len = strcspn(fw_name, "\n");
++	if (!len) {
++		dev_err(dev, "can't provide empty string for firmware name\n");
++		ret = -EINVAL;
++		goto out;
++	}
++
++	p = kstrndup(fw_name, len, GFP_KERNEL);
++	if (!p) {
++		ret = -ENOMEM;
++		goto out;
++	}
++
++	kfree(rproc->firmware);
++	rproc->firmware = p;
++
++out:
++	mutex_unlock(&rproc->lock);
++	return ret;
++}
++EXPORT_SYMBOL(rproc_set_firmware);
++
+ static int rproc_validate(struct rproc *rproc)
+ {
+ 	switch (rproc->state) {
+diff --git a/drivers/remoteproc/remoteproc_sysfs.c b/drivers/remoteproc/remoteproc_sysfs.c
+index d1cf7bf277c4..1dbef895e65e 100644
+--- a/drivers/remoteproc/remoteproc_sysfs.c
++++ b/drivers/remoteproc/remoteproc_sysfs.c
+@@ -154,38 +154,9 @@ static ssize_t firmware_store(struct device *dev,
+ 			      const char *buf, size_t count)
+ {
+ 	struct rproc *rproc = to_rproc(dev);
+-	char *p;
+-	int err, len = count;
++	int err;
+ 
+-	err = mutex_lock_interruptible(&rproc->lock);
+-	if (err) {
+-		dev_err(dev, "can't lock rproc %s: %d\n", rproc->name, err);
+-		return -EINVAL;
+-	}
+-
+-	if (rproc->state != RPROC_OFFLINE) {
+-		dev_err(dev, "can't change firmware while running\n");
+-		err = -EBUSY;
+-		goto out;
+-	}
+-
+-	len = strcspn(buf, "\n");
+-	if (!len) {
+-		dev_err(dev, "can't provide a NULL firmware\n");
+-		err = -EINVAL;
+-		goto out;
+-	}
+-
+-	p = kstrndup(buf, len, GFP_KERNEL);
+-	if (!p) {
+-		err = -ENOMEM;
+-		goto out;
+-	}
+-
+-	kfree(rproc->firmware);
+-	rproc->firmware = p;
+-out:
+-	mutex_unlock(&rproc->lock);
++	err = rproc_set_firmware(rproc, buf);
+ 
+ 	return err ? err : count;
+ }
+diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
+index 3fa3ba6498e8..e8ac041c64d9 100644
+--- a/include/linux/remoteproc.h
++++ b/include/linux/remoteproc.h
+@@ -653,6 +653,7 @@ rproc_of_resm_mem_entry_init(struct device *dev, u32 of_resm_idx, size_t len,
+ 
+ int rproc_boot(struct rproc *rproc);
+ void rproc_shutdown(struct rproc *rproc);
++int rproc_set_firmware(struct rproc *rproc, const char *fw_name);
+ void rproc_report_crash(struct rproc *rproc, enum rproc_crash_type type);
+ int rproc_coredump_add_segment(struct rproc *rproc, dma_addr_t da, size_t size);
+ int rproc_coredump_add_custom_segment(struct rproc *rproc,

board/PSG/iot2050/files/patches-5.10/0035-remoteproc-pru-Add-a-PRU-remoteproc-driver.patch

@@ -0,0 +1,525 @@
+From d375626600519e750876cafd521c7ea02072ccd2 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Tue, 8 Dec 2020 15:09:58 +0100
+Subject: [PATCH] remoteproc: pru: Add a PRU remoteproc driver
+
+The Programmable Real-Time Unit Subsystem (PRUSS) consists of
+dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs)
+for program execution. This patch adds a remoteproc platform
+driver for managing the individual PRU RISC cores life cycle.
+
+The PRUs do not have a unified address space (have an Instruction
+RAM and a primary Data RAM at both 0x0). The PRU remoteproc driver
+therefore uses a custom remoteproc core ELF loader ops. The added
+.da_to_va ops is only used to provide translations for the PRU
+Data RAMs. This remoteproc driver does not have support for error
+recovery and system suspend/resume features. Different compatibles
+are used to allow providing scalability for instance-specific device
+data if needed. The driver uses a default firmware-name retrieved
+from device-tree for each PRU core, and the firmwares are expected
+to be present in the standard Linux firmware search paths. They can
+also be adjusted by userspace if required through the sysfs interface
+provided by the remoteproc core.
+
+The PRU remoteproc driver uses a client-driven boot methodology: it
+does _not_ support auto-boot so that the PRU load and boot is dictated
+by the corresponding client drivers for achieving various usecases.
+This allows flexibility for the client drivers or applications to set
+a firmware name (if needed) based on their desired functionality and
+boot the PRU. The sysfs bind and unbind attributes have also been
+suppressed so that the PRU devices cannot be unbound and thereby
+shutdown a PRU from underneath a PRU client driver.
+
+The driver currently supports the AM335x, AM437x, AM57xx and 66AK2G
+SoCs, and support for other TI SoCs will be added in subsequent
+patches.
+
+Co-developed-by: Andrew F. Davis <afd@ti.com>
+Signed-off-by: Andrew F. Davis <afd@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Link: https://lore.kernel.org/r/20201208141002.17777-3-grzegorz.jaszczyk@linaro.org
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/Kconfig     |  12 +
+ drivers/remoteproc/Makefile    |   1 +
+ drivers/remoteproc/pru_rproc.c | 433 +++++++++++++++++++++++++++++++++
+ 3 files changed, 446 insertions(+)
+ create mode 100644 drivers/remoteproc/pru_rproc.c
+
+diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
+index d99548fb5dde..3e3865a7cd78 100644
+--- a/drivers/remoteproc/Kconfig
++++ b/drivers/remoteproc/Kconfig
+@@ -125,6 +125,18 @@ config KEYSTONE_REMOTEPROC
+ 	  It's safe to say N here if you're not interested in the Keystone
+ 	  DSPs or just want to use a bare minimum kernel.
+ 
++config PRU_REMOTEPROC
++	tristate "TI PRU remoteproc support"
++	depends on TI_PRUSS
++	default TI_PRUSS
++	help
++	  Support for TI PRU remote processors present within a PRU-ICSS
++	  subsystem via the remote processor framework.
++
++	  Say Y or M here to support the Programmable Realtime Unit (PRU)
++	  processors on various TI SoCs. It's safe to say N here if you're
++	  not interested in the PRU or if you are unsure.
++
+ config QCOM_PIL_INFO
+ 	tristate
+ 
+diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
+index da2ace4ec86c..bb26c9e4ef9c 100644
+--- a/drivers/remoteproc/Makefile
++++ b/drivers/remoteproc/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC)		+= omap_remoteproc.o
+ obj-$(CONFIG_WKUP_M3_RPROC)		+= wkup_m3_rproc.o
+ obj-$(CONFIG_DA8XX_REMOTEPROC)		+= da8xx_remoteproc.o
+ obj-$(CONFIG_KEYSTONE_REMOTEPROC)	+= keystone_remoteproc.o
++obj-$(CONFIG_PRU_REMOTEPROC)		+= pru_rproc.o
+ obj-$(CONFIG_QCOM_PIL_INFO)		+= qcom_pil_info.o
+ obj-$(CONFIG_QCOM_RPROC_COMMON)		+= qcom_common.o
+ obj-$(CONFIG_QCOM_Q6V5_COMMON)		+= qcom_q6v5.o
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+new file mode 100644
+index 000000000000..d33392bbd8af
+--- /dev/null
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -0,0 +1,433 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * PRU-ICSS remoteproc driver for various TI SoCs
++ *
++ * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/
++ *
++ * Author(s):
++ *	Suman Anna <s-anna@ti.com>
++ *	Andrew F. Davis <afd@ti.com>
++ *	Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org> for Texas Instruments
++ */
++
++#include <linux/bitops.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/pruss_driver.h>
++#include <linux/remoteproc.h>
++
++#include "remoteproc_internal.h"
++#include "remoteproc_elf_helpers.h"
++
++/* PRU_ICSS_PRU_CTRL registers */
++#define PRU_CTRL_CTRL		0x0000
++#define PRU_CTRL_STS		0x0004
++
++/* CTRL register bit-fields */
++#define CTRL_CTRL_SOFT_RST_N	BIT(0)
++#define CTRL_CTRL_EN		BIT(1)
++#define CTRL_CTRL_SLEEPING	BIT(2)
++#define CTRL_CTRL_CTR_EN	BIT(3)
++#define CTRL_CTRL_SINGLE_STEP	BIT(8)
++#define CTRL_CTRL_RUNSTATE	BIT(15)
++
++/* PRU Core IRAM address masks */
++#define PRU_IRAM_ADDR_MASK	0x3ffff
++#define PRU0_IRAM_ADDR_MASK	0x34000
++#define PRU1_IRAM_ADDR_MASK	0x38000
++
++/* PRU device addresses for various type of PRU RAMs */
++#define PRU_IRAM_DA	0	/* Instruction RAM */
++#define PRU_PDRAM_DA	0	/* Primary Data RAM */
++#define PRU_SDRAM_DA	0x2000	/* Secondary Data RAM */
++#define PRU_SHRDRAM_DA	0x10000 /* Shared Data RAM */
++
++/**
++ * enum pru_iomem - PRU core memory/register range identifiers
++ *
++ * @PRU_IOMEM_IRAM: PRU Instruction RAM range
++ * @PRU_IOMEM_CTRL: PRU Control register range
++ * @PRU_IOMEM_DEBUG: PRU Debug register range
++ * @PRU_IOMEM_MAX: just keep this one at the end
++ */
++enum pru_iomem {
++	PRU_IOMEM_IRAM = 0,
++	PRU_IOMEM_CTRL,
++	PRU_IOMEM_DEBUG,
++	PRU_IOMEM_MAX,
++};
++
++/**
++ * struct pru_rproc - PRU remoteproc structure
++ * @id: id of the PRU core within the PRUSS
++ * @dev: PRU core device pointer
++ * @pruss: back-reference to parent PRUSS structure
++ * @rproc: remoteproc pointer for this PRU core
++ * @mem_regions: data for each of the PRU memory regions
++ * @fw_name: name of firmware image used during loading
++ */
++struct pru_rproc {
++	int id;
++	struct device *dev;
++	struct pruss *pruss;
++	struct rproc *rproc;
++	struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
++	const char *fw_name;
++};
++
++static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg)
++{
++	return readl_relaxed(pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
++}
++
++static inline
++void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
++{
++	writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
++}
++
++static int pru_rproc_start(struct rproc *rproc)
++{
++	struct device *dev = &rproc->dev;
++	struct pru_rproc *pru = rproc->priv;
++	u32 val;
++
++	dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n",
++		pru->id, (rproc->bootaddr >> 2));
++
++	val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16);
++	pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
++
++	return 0;
++}
++
++static int pru_rproc_stop(struct rproc *rproc)
++{
++	struct device *dev = &rproc->dev;
++	struct pru_rproc *pru = rproc->priv;
++	u32 val;
++
++	dev_dbg(dev, "stopping PRU%d\n", pru->id);
++
++	val = pru_control_read_reg(pru, PRU_CTRL_CTRL);
++	val &= ~CTRL_CTRL_EN;
++	pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
++
++	return 0;
++}
++
++/*
++ * Convert PRU device address (data spaces only) to kernel virtual address.
++ *
++ * Each PRU has access to all data memories within the PRUSS, accessible at
++ * different ranges. So, look through both its primary and secondary Data
++ * RAMs as well as any shared Data RAM to convert a PRU device address to
++ * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data
++ * RAM1 is primary Data RAM for PRU1.
++ */
++static void *pru_d_da_to_va(struct pru_rproc *pru, u32 da, size_t len)
++{
++	struct pruss_mem_region dram0, dram1, shrd_ram;
++	struct pruss *pruss = pru->pruss;
++	u32 offset;
++	void *va = NULL;
++
++	if (len == 0)
++		return NULL;
++
++	dram0 = pruss->mem_regions[PRUSS_MEM_DRAM0];
++	dram1 = pruss->mem_regions[PRUSS_MEM_DRAM1];
++	/* PRU1 has its local RAM addresses reversed */
++	if (pru->id == 1)
++		swap(dram0, dram1);
++	shrd_ram = pruss->mem_regions[PRUSS_MEM_SHRD_RAM2];
++
++	if (da >= PRU_PDRAM_DA && da + len <= PRU_PDRAM_DA + dram0.size) {
++		offset = da - PRU_PDRAM_DA;
++		va = (__force void *)(dram0.va + offset);
++	} else if (da >= PRU_SDRAM_DA &&
++		   da + len <= PRU_SDRAM_DA + dram1.size) {
++		offset = da - PRU_SDRAM_DA;
++		va = (__force void *)(dram1.va + offset);
++	} else if (da >= PRU_SHRDRAM_DA &&
++		   da + len <= PRU_SHRDRAM_DA + shrd_ram.size) {
++		offset = da - PRU_SHRDRAM_DA;
++		va = (__force void *)(shrd_ram.va + offset);
++	}
++
++	return va;
++}
++
++/*
++ * Convert PRU device address (instruction space) to kernel virtual address.
++ *
++ * A PRU does not have an unified address space. Each PRU has its very own
++ * private Instruction RAM, and its device address is identical to that of
++ * its primary Data RAM device address.
++ */
++static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len)
++{
++	u32 offset;
++	void *va = NULL;
++
++	if (len == 0)
++		return NULL;
++
++	if (da >= PRU_IRAM_DA &&
++	    da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) {
++		offset = da - PRU_IRAM_DA;
++		va = (__force void *)(pru->mem_regions[PRU_IOMEM_IRAM].va +
++				      offset);
++	}
++
++	return va;
++}
++
++/*
++ * Provide address translations for only PRU Data RAMs through the remoteproc
++ * core for any PRU client drivers. The PRU Instruction RAM access is restricted
++ * only to the PRU loader code.
++ */
++static void *pru_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len)
++{
++	struct pru_rproc *pru = rproc->priv;
++
++	return pru_d_da_to_va(pru, da, len);
++}
++
++/* PRU-specific address translator used by PRU loader. */
++static void *pru_da_to_va(struct rproc *rproc, u64 da, size_t len, bool is_iram)
++{
++	struct pru_rproc *pru = rproc->priv;
++	void *va;
++
++	if (is_iram)
++		va = pru_i_da_to_va(pru, da, len);
++	else
++		va = pru_d_da_to_va(pru, da, len);
++
++	return va;
++}
++
++static struct rproc_ops pru_rproc_ops = {
++	.start		= pru_rproc_start,
++	.stop		= pru_rproc_stop,
++	.da_to_va	= pru_rproc_da_to_va,
++};
++
++static int
++pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw)
++{
++	struct device *dev = &rproc->dev;
++	struct elf32_hdr *ehdr;
++	struct elf32_phdr *phdr;
++	int i, ret = 0;
++	const u8 *elf_data = fw->data;
++
++	ehdr = (struct elf32_hdr *)elf_data;
++	phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff);
++
++	/* go through the available ELF segments */
++	for (i = 0; i < ehdr->e_phnum; i++, phdr++) {
++		u32 da = phdr->p_paddr;
++		u32 memsz = phdr->p_memsz;
++		u32 filesz = phdr->p_filesz;
++		u32 offset = phdr->p_offset;
++		bool is_iram;
++		void *ptr;
++
++		if (phdr->p_type != PT_LOAD || !filesz)
++			continue;
++
++		dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n",
++			phdr->p_type, da, memsz, filesz);
++
++		if (filesz > memsz) {
++			dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x\n",
++				filesz, memsz);
++			ret = -EINVAL;
++			break;
++		}
++
++		if (offset + filesz > fw->size) {
++			dev_err(dev, "truncated fw: need 0x%x avail 0x%zx\n",
++				offset + filesz, fw->size);
++			ret = -EINVAL;
++			break;
++		}
++
++		/* grab the kernel address for this device address */
++		is_iram = phdr->p_flags & PF_X;
++		ptr = pru_da_to_va(rproc, da, memsz, is_iram);
++		if (!ptr) {
++			dev_err(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz);
++			ret = -EINVAL;
++			break;
++		}
++
++		memcpy(ptr, elf_data + phdr->p_offset, filesz);
++
++		/* skip the memzero logic performed by remoteproc ELF loader */
++	}
++
++	return ret;
++}
++
++/*
++ * Use a custom parse_fw callback function for dealing with PRU firmware
++ * specific sections.
++ */
++static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
++{
++	int ret;
++
++	/* load optional rsc table */
++	ret = rproc_elf_load_rsc_table(rproc, fw);
++	if (ret == -EINVAL)
++		dev_dbg(&rproc->dev, "no resource table found for this fw\n");
++	else if (ret)
++		return ret;
++
++	return 0;
++}
++
++/*
++ * Compute PRU id based on the IRAM addresses. The PRU IRAMs are
++ * always at a particular offset within the PRUSS address space.
++ */
++static int pru_rproc_set_id(struct pru_rproc *pru)
++{
++	int ret = 0;
++
++	switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) {
++	case PRU0_IRAM_ADDR_MASK:
++		pru->id = 0;
++		break;
++	case PRU1_IRAM_ADDR_MASK:
++		pru->id = 1;
++		break;
++	default:
++		ret = -EINVAL;
++	}
++
++	return ret;
++}
++
++static int pru_rproc_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct platform_device *ppdev = to_platform_device(dev->parent);
++	struct pru_rproc *pru;
++	const char *fw_name;
++	struct rproc *rproc = NULL;
++	struct resource *res;
++	int i, ret;
++	const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" };
++
++	ret = of_property_read_string(np, "firmware-name", &fw_name);
++	if (ret) {
++		dev_err(dev, "unable to retrieve firmware-name %d\n", ret);
++		return ret;
++	}
++
++	rproc = devm_rproc_alloc(dev, pdev->name, &pru_rproc_ops, fw_name,
++				 sizeof(*pru));
++	if (!rproc) {
++		dev_err(dev, "rproc_alloc failed\n");
++		return -ENOMEM;
++	}
++	/* use a custom load function to deal with PRU-specific quirks */
++	rproc->ops->load = pru_rproc_load_elf_segments;
++
++	/* use a custom parse function to deal with PRU-specific resources */
++	rproc->ops->parse_fw = pru_rproc_parse_fw;
++
++	/* error recovery is not supported for PRUs */
++	rproc->recovery_disabled = true;
++
++	/*
++	 * rproc_add will auto-boot the processor normally, but this is not
++	 * desired with PRU client driven boot-flow methodology. A PRU
++	 * application/client driver will boot the corresponding PRU
++	 * remote-processor as part of its state machine either through the
++	 * remoteproc sysfs interface or through the equivalent kernel API.
++	 */
++	rproc->auto_boot = false;
++
++	pru = rproc->priv;
++	pru->dev = dev;
++	pru->pruss = platform_get_drvdata(ppdev);
++	pru->rproc = rproc;
++	pru->fw_name = fw_name;
++
++	for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
++		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
++						   mem_names[i]);
++		pru->mem_regions[i].va = devm_ioremap_resource(dev, res);
++		if (IS_ERR(pru->mem_regions[i].va)) {
++			dev_err(dev, "failed to parse and map memory resource %d %s\n",
++				i, mem_names[i]);
++			ret = PTR_ERR(pru->mem_regions[i].va);
++			return ret;
++		}
++		pru->mem_regions[i].pa = res->start;
++		pru->mem_regions[i].size = resource_size(res);
++
++		dev_dbg(dev, "memory %8s: pa %pa size 0x%zx va %pK\n",
++			mem_names[i], &pru->mem_regions[i].pa,
++			pru->mem_regions[i].size, pru->mem_regions[i].va);
++	}
++
++	ret = pru_rproc_set_id(pru);
++	if (ret < 0)
++		return ret;
++
++	platform_set_drvdata(pdev, rproc);
++
++	ret = devm_rproc_add(dev, pru->rproc);
++	if (ret) {
++		dev_err(dev, "rproc_add failed: %d\n", ret);
++		return ret;
++	}
++
++	dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np);
++
++	return 0;
++}
++
++static int pru_rproc_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct rproc *rproc = platform_get_drvdata(pdev);
++
++	dev_dbg(dev, "%s: removing rproc %s\n", __func__, rproc->name);
++
++	return 0;
++}
++
++static const struct of_device_id pru_rproc_match[] = {
++	{ .compatible = "ti,am3356-pru", },
++	{ .compatible = "ti,am4376-pru", },
++	{ .compatible = "ti,am5728-pru", },
++	{ .compatible = "ti,k2g-pru",    },
++	{},
++};
++MODULE_DEVICE_TABLE(of, pru_rproc_match);
++
++static struct platform_driver pru_rproc_driver = {
++	.driver = {
++		.name   = "pru-rproc",
++		.of_match_table = pru_rproc_match,
++		.suppress_bind_attrs = true,
++	},
++	.probe  = pru_rproc_probe,
++	.remove = pru_rproc_remove,
++};
++module_platform_driver(pru_rproc_driver);
++
++MODULE_AUTHOR("Suman Anna <s-anna@ti.com>");
++MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
++MODULE_AUTHOR("Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>");
++MODULE_DESCRIPTION("PRU-ICSS Remote Processor Driver");
++MODULE_LICENSE("GPL v2");

board/PSG/iot2050/files/patches-5.10/0036-remoteproc-pru-Add-support-for-PRU-specific-interrup.patch

@@ -0,0 +1,353 @@
+From 22e43fbf99474ff85df13755b3654c23686267c7 Mon Sep 17 00:00:00 2001
+From: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Date: Tue, 8 Dec 2020 15:09:59 +0100
+Subject: [PATCH] remoteproc: pru: Add support for PRU specific interrupt
+ configuration
+
+The firmware blob can contain optional ELF sections: .resource_table
+section and .pru_irq_map one. The second one contains the PRUSS
+interrupt mapping description, which needs to be setup before powering
+on the PRU core. To avoid RAM wastage this ELF section is not mapped to
+any ELF segment (by the firmware linker) and therefore is not loaded to
+PRU memory.
+
+The PRU interrupt configuration is handled within the PRUSS INTC irqchip
+driver and leverages the system events to interrupt channels and host
+interrupts mapping configuration. Relevant irq routing information is
+passed through a special .pru_irq_map ELF section (for interrupts routed
+to and used by PRU cores) or via the PRU application's device tree node
+(for interrupts routed to and used by the main CPU). The mappings are
+currently programmed during the booting/shutdown of the PRU.
+
+The interrupt configuration passed through .pru_irq_map ELF section is
+optional. It varies on specific firmware functionality and therefore
+have to be unwinded during PRU stop and performed again during
+PRU start.
+
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Link: https://lore.kernel.org/r/20201208141002.17777-4-grzegorz.jaszczyk@linaro.org
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 181 +++++++++++++++++++++++++++++++++
+ drivers/remoteproc/pru_rproc.h |  46 +++++++++
+ 2 files changed, 227 insertions(+)
+ create mode 100644 drivers/remoteproc/pru_rproc.h
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index d33392bbd8af..72e64d15f0dc 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -11,13 +11,16 @@
+  */
+ 
+ #include <linux/bitops.h>
++#include <linux/irqdomain.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
++#include <linux/of_irq.h>
+ #include <linux/pruss_driver.h>
+ #include <linux/remoteproc.h>
+ 
+ #include "remoteproc_internal.h"
+ #include "remoteproc_elf_helpers.h"
++#include "pru_rproc.h"
+ 
+ /* PRU_ICSS_PRU_CTRL registers */
+ #define PRU_CTRL_CTRL		0x0000
+@@ -42,6 +45,8 @@
+ #define PRU_SDRAM_DA	0x2000	/* Secondary Data RAM */
+ #define PRU_SHRDRAM_DA	0x10000 /* Shared Data RAM */
+ 
++#define MAX_PRU_SYS_EVENTS 160
++
+ /**
+  * enum pru_iomem - PRU core memory/register range identifiers
+  *
+@@ -65,6 +70,10 @@ enum pru_iomem {
+  * @rproc: remoteproc pointer for this PRU core
+  * @mem_regions: data for each of the PRU memory regions
+  * @fw_name: name of firmware image used during loading
++ * @mapped_irq: virtual interrupt numbers of created fw specific mapping
++ * @pru_interrupt_map: pointer to interrupt mapping description (firmware)
++ * @pru_interrupt_map_sz: pru_interrupt_map size
++ * @evt_count: number of mapped events
+  */
+ struct pru_rproc {
+ 	int id;
+@@ -73,6 +82,10 @@ struct pru_rproc {
+ 	struct rproc *rproc;
+ 	struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
+ 	const char *fw_name;
++	unsigned int *mapped_irq;
++	struct pru_irq_rsc *pru_interrupt_map;
++	size_t pru_interrupt_map_sz;
++	u8 evt_count;
+ };
+ 
+ static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg)
+@@ -86,15 +99,108 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
+ 	writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
+ }
+ 
++static void pru_dispose_irq_mapping(struct pru_rproc *pru)
++{
++	while (pru->evt_count--) {
++		if (pru->mapped_irq[pru->evt_count] > 0)
++			irq_dispose_mapping(pru->mapped_irq[pru->evt_count]);
++	}
++
++	kfree(pru->mapped_irq);
++}
++
++/*
++ * Parse the custom PRU interrupt map resource and configure the INTC
++ * appropriately.
++ */
++static int pru_handle_intrmap(struct rproc *rproc)
++{
++	struct device *dev = rproc->dev.parent;
++	struct pru_rproc *pru = rproc->priv;
++	struct pru_irq_rsc *rsc = pru->pru_interrupt_map;
++	struct irq_fwspec fwspec;
++	struct device_node *irq_parent;
++	int i, ret = 0;
++
++	/* not having pru_interrupt_map is not an error */
++	if (!rsc)
++		return 0;
++
++	/* currently supporting only type 0 */
++	if (rsc->type != 0) {
++		dev_err(dev, "unsupported rsc type: %d\n", rsc->type);
++		return -EINVAL;
++	}
++
++	if (rsc->num_evts > MAX_PRU_SYS_EVENTS)
++		return -EINVAL;
++
++	if (sizeof(*rsc) + rsc->num_evts * sizeof(struct pruss_int_map) !=
++	    pru->pru_interrupt_map_sz)
++		return -EINVAL;
++
++	pru->evt_count = rsc->num_evts;
++	pru->mapped_irq = kcalloc(pru->evt_count, sizeof(unsigned int),
++				  GFP_KERNEL);
++	if (!pru->mapped_irq)
++		return -ENOMEM;
++
++	/*
++	 * parse and fill in system event to interrupt channel and
++	 * channel-to-host mapping
++	 */
++	irq_parent = of_irq_find_parent(pru->dev->of_node);
++	if (!irq_parent) {
++		kfree(pru->mapped_irq);
++		return -ENODEV;
++	}
++
++	fwspec.fwnode = of_node_to_fwnode(irq_parent);
++	fwspec.param_count = 3;
++	for (i = 0; i < pru->evt_count; i++) {
++		fwspec.param[0] = rsc->pru_intc_map[i].event;
++		fwspec.param[1] = rsc->pru_intc_map[i].chnl;
++		fwspec.param[2] = rsc->pru_intc_map[i].host;
++
++		dev_dbg(dev, "mapping%d: event %d, chnl %d, host %d\n",
++			i, fwspec.param[0], fwspec.param[1], fwspec.param[2]);
++
++		pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec);
++		if (!pru->mapped_irq[i]) {
++			dev_err(dev, "failed to get virq\n");
++			ret = pru->mapped_irq[i];
++			goto map_fail;
++		}
++	}
++
++	return ret;
++
++map_fail:
++	pru_dispose_irq_mapping(pru);
++
++	return ret;
++}
++
+ static int pru_rproc_start(struct rproc *rproc)
+ {
+ 	struct device *dev = &rproc->dev;
+ 	struct pru_rproc *pru = rproc->priv;
+ 	u32 val;
++	int ret;
+ 
+ 	dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n",
+ 		pru->id, (rproc->bootaddr >> 2));
+ 
++	ret = pru_handle_intrmap(rproc);
++	/*
++	 * reset references to pru interrupt map - they will stop being valid
++	 * after rproc_start returns
++	 */
++	pru->pru_interrupt_map = NULL;
++	pru->pru_interrupt_map_sz = 0;
++	if (ret)
++		return ret;
++
+ 	val = CTRL_CTRL_EN | ((rproc->bootaddr >> 2) << 16);
+ 	pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
+ 
+@@ -113,6 +219,10 @@ static int pru_rproc_stop(struct rproc *rproc)
+ 	val &= ~CTRL_CTRL_EN;
+ 	pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
+ 
++	/* dispose irq mapping - new firmware can provide new mapping */
++	if (pru->mapped_irq)
++		pru_dispose_irq_mapping(pru);
++
+ 	return 0;
+ }
+ 
+@@ -273,12 +383,70 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw)
+ 	return ret;
+ }
+ 
++static const void *
++pru_rproc_find_interrupt_map(struct device *dev, const struct firmware *fw)
++{
++	struct elf32_shdr *shdr, *name_table_shdr;
++	const char *name_table;
++	const u8 *elf_data = fw->data;
++	struct elf32_hdr *ehdr = (struct elf32_hdr *)elf_data;
++	u16 shnum = ehdr->e_shnum;
++	u16 shstrndx = ehdr->e_shstrndx;
++	int i;
++
++	/* first, get the section header */
++	shdr = (struct elf32_shdr *)(elf_data + ehdr->e_shoff);
++	/* compute name table section header entry in shdr array */
++	name_table_shdr = shdr + shstrndx;
++	/* finally, compute the name table section address in elf */
++	name_table = elf_data + name_table_shdr->sh_offset;
++
++	for (i = 0; i < shnum; i++, shdr++) {
++		u32 size = shdr->sh_size;
++		u32 offset = shdr->sh_offset;
++		u32 name = shdr->sh_name;
++
++		if (strcmp(name_table + name, ".pru_irq_map"))
++			continue;
++
++		/* make sure we have the entire irq map */
++		if (offset + size > fw->size || offset + size < size) {
++			dev_err(dev, ".pru_irq_map section truncated\n");
++			return ERR_PTR(-EINVAL);
++		}
++
++		/* make sure irq map has at least the header */
++		if (sizeof(struct pru_irq_rsc) > size) {
++			dev_err(dev, "header-less .pru_irq_map section\n");
++			return ERR_PTR(-EINVAL);
++		}
++
++		return shdr;
++	}
++
++	dev_dbg(dev, "no .pru_irq_map section found for this fw\n");
++
++	return NULL;
++}
++
+ /*
+  * Use a custom parse_fw callback function for dealing with PRU firmware
+  * specific sections.
++ *
++ * The firmware blob can contain optional ELF sections: .resource_table section
++ * and .pru_irq_map one. The second one contains the PRUSS interrupt mapping
++ * description, which needs to be setup before powering on the PRU core. To
++ * avoid RAM wastage this ELF section is not mapped to any ELF segment (by the
++ * firmware linker) and therefore is not loaded to PRU memory.
+  */
+ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
+ {
++	struct device *dev = &rproc->dev;
++	struct pru_rproc *pru = rproc->priv;
++	const u8 *elf_data = fw->data;
++	const void *shdr;
++	u8 class = fw_elf_get_class(fw);
++	u64 sh_offset;
+ 	int ret;
+ 
+ 	/* load optional rsc table */
+@@ -288,6 +456,19 @@ static int pru_rproc_parse_fw(struct rproc *rproc, const struct firmware *fw)
+ 	else if (ret)
+ 		return ret;
+ 
++	/* find .pru_interrupt_map section, not having it is not an error */
++	shdr = pru_rproc_find_interrupt_map(dev, fw);
++	if (IS_ERR(shdr))
++		return PTR_ERR(shdr);
++
++	if (!shdr)
++		return 0;
++
++	/* preserve pointer to PRU interrupt map together with it size */
++	sh_offset = elf_shdr_get_sh_offset(class, shdr);
++	pru->pru_interrupt_map = (struct pru_irq_rsc *)(elf_data + sh_offset);
++	pru->pru_interrupt_map_sz = elf_shdr_get_sh_size(class, shdr);
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/remoteproc/pru_rproc.h b/drivers/remoteproc/pru_rproc.h
+new file mode 100644
+index 000000000000..8ee9c3171610
+--- /dev/null
++++ b/drivers/remoteproc/pru_rproc.h
+@@ -0,0 +1,46 @@
++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
++/*
++ * PRUSS Remote Processor specific types
++ *
++ * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/
++ *	Suman Anna <s-anna@ti.com>
++ */
++
++#ifndef _PRU_RPROC_H_
++#define _PRU_RPROC_H_
++
++/**
++ * struct pruss_int_map - PRU system events _to_ channel and host mapping
++ * @event: number of the system event
++ * @chnl: channel number assigned to a given @event
++ * @host: host number assigned to a given @chnl
++ *
++ * PRU system events are mapped to channels, and these channels are mapped
++ * to host interrupts. Events can be mapped to channels in a one-to-one or
++ * many-to-one ratio (multiple events per channel), and channels can be
++ * mapped to host interrupts in a one-to-one or many-to-one ratio (multiple
++ * channels per interrupt).
++ */
++struct pruss_int_map {
++	u8 event;
++	u8 chnl;
++	u8 host;
++};
++
++/**
++ * struct pru_irq_rsc - PRU firmware section header for IRQ data
++ * @type: resource type
++ * @num_evts: number of described events
++ * @pru_intc_map: PRU interrupt routing description
++ *
++ * The PRU firmware blob can contain optional .pru_irq_map ELF section, which
++ * provides the PRUSS interrupt mapping description. The pru_irq_rsc struct
++ * describes resource entry format.
++ */
++struct pru_irq_rsc {
++	u8 type;
++	u8 num_evts;
++	struct pruss_int_map pru_intc_map[];
++} __packed;
++
++#endif	/* _PRU_RPROC_H_ */

board/PSG/iot2050/files/patches-5.10/0037-remoteproc-pru-Add-pru-specific-debugfs-support.patch

@@ -0,0 +1,224 @@
+From 92d306c8632ef5eaee57fe5b8577cb039952ecde Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Tue, 8 Dec 2020 15:10:00 +0100
+Subject: [PATCH] remoteproc: pru: Add pru-specific debugfs support
+
+The remoteproc core creates certain standard debugfs entries,
+that does not give a whole lot of useful information for the
+PRUs. The PRU remoteproc driver is enhanced to add additional
+debugfs entries for PRU. These will be auto-cleaned up when
+the parent rproc debug directory is removed.
+
+The enhanced debugfs support adds two new entries: 'regs' and
+'single_step'. The 'regs' dumps out the useful CTRL sub-module
+registers as well as each of the 32 GPREGs and CT_REGs registers.
+The GPREGs and CT_REGs though are printed only when the PRU is
+halted and accessible as per the IP design.
+
+The 'single_step' utilizes the single-step execution of the PRU
+cores. Writing a non-zero value performs a single step, and a
+zero value restores the PRU to execute in the same mode as the
+mode before the first single step. (note: if the PRU is halted
+because of a halt instruction, then no change occurs).
+
+Logic for setting the PC and jumping over a halt instruction shall
+be added in the future.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Link: https://lore.kernel.org/r/20201208141002.17777-5-grzegorz.jaszczyk@linaro.org
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 136 +++++++++++++++++++++++++++++++++
+ 1 file changed, 136 insertions(+)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 72e64d15f0dc..59240fd82f56 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -11,6 +11,7 @@
+  */
+ 
+ #include <linux/bitops.h>
++#include <linux/debugfs.h>
+ #include <linux/irqdomain.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+@@ -25,6 +26,13 @@
+ /* PRU_ICSS_PRU_CTRL registers */
+ #define PRU_CTRL_CTRL		0x0000
+ #define PRU_CTRL_STS		0x0004
++#define PRU_CTRL_WAKEUP_EN	0x0008
++#define PRU_CTRL_CYCLE		0x000C
++#define PRU_CTRL_STALL		0x0010
++#define PRU_CTRL_CTBIR0		0x0020
++#define PRU_CTRL_CTBIR1		0x0024
++#define PRU_CTRL_CTPPR0		0x0028
++#define PRU_CTRL_CTPPR1		0x002C
+ 
+ /* CTRL register bit-fields */
+ #define CTRL_CTRL_SOFT_RST_N	BIT(0)
+@@ -34,6 +42,10 @@
+ #define CTRL_CTRL_SINGLE_STEP	BIT(8)
+ #define CTRL_CTRL_RUNSTATE	BIT(15)
+ 
++/* PRU_ICSS_PRU_DEBUG registers */
++#define PRU_DEBUG_GPREG(x)	(0x0000 + (x) * 4)
++#define PRU_DEBUG_CT_REG(x)	(0x0080 + (x) * 4)
++
+ /* PRU Core IRAM address masks */
+ #define PRU_IRAM_ADDR_MASK	0x3ffff
+ #define PRU0_IRAM_ADDR_MASK	0x34000
+@@ -73,6 +85,8 @@ enum pru_iomem {
+  * @mapped_irq: virtual interrupt numbers of created fw specific mapping
+  * @pru_interrupt_map: pointer to interrupt mapping description (firmware)
+  * @pru_interrupt_map_sz: pru_interrupt_map size
++ * @dbg_single_step: debug state variable to set PRU into single step mode
++ * @dbg_continuous: debug state variable to restore PRU execution mode
+  * @evt_count: number of mapped events
+  */
+ struct pru_rproc {
+@@ -85,6 +99,8 @@ struct pru_rproc {
+ 	unsigned int *mapped_irq;
+ 	struct pru_irq_rsc *pru_interrupt_map;
+ 	size_t pru_interrupt_map_sz;
++	u32 dbg_single_step;
++	u32 dbg_continuous;
+ 	u8 evt_count;
+ };
+ 
+@@ -99,6 +115,124 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
+ 	writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
+ }
+ 
++static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg)
++{
++	return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg);
++}
++
++static int regs_show(struct seq_file *s, void *data)
++{
++	struct rproc *rproc = s->private;
++	struct pru_rproc *pru = rproc->priv;
++	int i, nregs = 32;
++	u32 pru_sts;
++	int pru_is_running;
++
++	seq_puts(s, "============== Control Registers ==============\n");
++	seq_printf(s, "CTRL      := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_CTRL));
++	pru_sts = pru_control_read_reg(pru, PRU_CTRL_STS);
++	seq_printf(s, "STS (PC)  := 0x%08x (0x%08x)\n", pru_sts, pru_sts << 2);
++	seq_printf(s, "WAKEUP_EN := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_WAKEUP_EN));
++	seq_printf(s, "CYCLE     := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_CYCLE));
++	seq_printf(s, "STALL     := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_STALL));
++	seq_printf(s, "CTBIR0    := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_CTBIR0));
++	seq_printf(s, "CTBIR1    := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_CTBIR1));
++	seq_printf(s, "CTPPR0    := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_CTPPR0));
++	seq_printf(s, "CTPPR1    := 0x%08x\n",
++		   pru_control_read_reg(pru, PRU_CTRL_CTPPR1));
++
++	seq_puts(s, "=============== Debug Registers ===============\n");
++	pru_is_running = pru_control_read_reg(pru, PRU_CTRL_CTRL) &
++				CTRL_CTRL_RUNSTATE;
++	if (pru_is_running) {
++		seq_puts(s, "PRU is executing, cannot print/access debug registers.\n");
++		return 0;
++	}
++
++	for (i = 0; i < nregs; i++) {
++		seq_printf(s, "GPREG%-2d := 0x%08x\tCT_REG%-2d := 0x%08x\n",
++			   i, pru_debug_read_reg(pru, PRU_DEBUG_GPREG(i)),
++			   i, pru_debug_read_reg(pru, PRU_DEBUG_CT_REG(i)));
++	}
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(regs);
++
++/*
++ * Control PRU single-step mode
++ *
++ * This is a debug helper function used for controlling the single-step
++ * mode of the PRU. The PRU Debug registers are not accessible when the
++ * PRU is in RUNNING state.
++ *
++ * Writing a non-zero value sets the PRU into single-step mode irrespective
++ * of its previous state. The PRU mode is saved only on the first set into
++ * a single-step mode. Writing a zero value will restore the PRU into its
++ * original mode.
++ */
++static int pru_rproc_debug_ss_set(void *data, u64 val)
++{
++	struct rproc *rproc = data;
++	struct pru_rproc *pru = rproc->priv;
++	u32 reg_val;
++
++	val = val ? 1 : 0;
++	if (!val && !pru->dbg_single_step)
++		return 0;
++
++	reg_val = pru_control_read_reg(pru, PRU_CTRL_CTRL);
++
++	if (val && !pru->dbg_single_step)
++		pru->dbg_continuous = reg_val;
++
++	if (val)
++		reg_val |= CTRL_CTRL_SINGLE_STEP | CTRL_CTRL_EN;
++	else
++		reg_val = pru->dbg_continuous;
++
++	pru->dbg_single_step = val;
++	pru_control_write_reg(pru, PRU_CTRL_CTRL, reg_val);
++
++	return 0;
++}
++
++static int pru_rproc_debug_ss_get(void *data, u64 *val)
++{
++	struct rproc *rproc = data;
++	struct pru_rproc *pru = rproc->priv;
++
++	*val = pru->dbg_single_step;
++
++	return 0;
++}
++DEFINE_SIMPLE_ATTRIBUTE(pru_rproc_debug_ss_fops, pru_rproc_debug_ss_get,
++			pru_rproc_debug_ss_set, "%llu\n");
++
++/*
++ * Create PRU-specific debugfs entries
++ *
++ * The entries are created only if the parent remoteproc debugfs directory
++ * exists, and will be cleaned up by the remoteproc core.
++ */
++static void pru_rproc_create_debug_entries(struct rproc *rproc)
++{
++	if (!rproc->dbg_dir)
++		return;
++
++	debugfs_create_file("regs", 0400, rproc->dbg_dir,
++			    rproc, &regs_fops);
++	debugfs_create_file("single_step", 0600, rproc->dbg_dir,
++			    rproc, &pru_rproc_debug_ss_fops);
++}
++
+ static void pru_dispose_irq_mapping(struct pru_rproc *pru)
+ {
+ 	while (pru->evt_count--) {
+@@ -572,6 +706,8 @@ static int pru_rproc_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
++	pru_rproc_create_debug_entries(rproc);
++
+ 	dev_dbg(dev, "PRU rproc node %pOF probed successfully\n", np);
+ 
+ 	return 0;

board/PSG/iot2050/files/patches-5.10/0038-remoteproc-pru-Add-support-for-various-PRU-cores-on-.patch

@@ -0,0 +1,295 @@
+From fb4549d6687db66b009bcd7f83c648750fd885c6 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Tue, 8 Dec 2020 15:10:01 +0100
+Subject: [PATCH] remoteproc: pru: Add support for various PRU cores on K3
+ AM65x SoCs
+
+The K3 AM65x family of SoCs have the next generation of the PRU-ICSS
+processor subsystem, commonly referred to as ICSSG. Each ICSSG processor
+subsystem on AM65x SR1.0 contains two primary PRU cores and two new
+auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised
+ICSSG IP that is based off the subsequent IP revision used on J721E
+SoCs. This IP instance has two new custom auxiliary PRU cores called
+Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs.
+
+Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than
+a PRU), Control and debug feature sets, but is different in terms of
+sub-modules integrated around it and does not have the full capabilities
+associated with a PRU core. The RTU core is typically used to aid a
+PRU core in accelerating data transfers, while the Tx_PRU cores is
+normally used to control the TX L2 FIFO if enabled in Ethernet
+applications. Both can also be used to run independent applications.
+The RTU and Tx_PRU cores though share the same Data RAMs as the PRU
+cores, so the memories have to be partitioned carefully between different
+applications. The new cores also support a new sub-module called Task
+Manager to support two different context thread executions.
+
+Enhance the existing PRU remoteproc driver to support these new PRU, RTU
+and Tx PRU cores by using specific compatibles. The initial names for the
+firmware images for each PRU core are retrieved from DT nodes, and can
+be adjusted through sysfs if required.
+
+The PRU remoteproc driver has to be specifically modified to use a
+custom memcpy function within its ELF loader implementation for these
+new cores in order to overcome a limitation with copying data into each
+of the core's IRAM memories. These memory ports support only 4-byte
+writes, and any sub-word order byte writes clear out the remaining
+bytes other than the bytes being written within the containing word.
+The default ARM64 memcpy also cannot be used as it throws an exception
+when the preferred 8-byte copy operation is attempted. This choice is
+made by using a state flag that is set only on K3 SoCs.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Link: https://lore.kernel.org/r/20201208141002.17777-6-grzegorz.jaszczyk@linaro.org
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 140 ++++++++++++++++++++++++++++++---
+ 1 file changed, 131 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 59240fd82f56..421ebbc1c02d 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -46,10 +46,14 @@
+ #define PRU_DEBUG_GPREG(x)	(0x0000 + (x) * 4)
+ #define PRU_DEBUG_CT_REG(x)	(0x0080 + (x) * 4)
+ 
+-/* PRU Core IRAM address masks */
++/* PRU/RTU/Tx_PRU Core IRAM address masks */
+ #define PRU_IRAM_ADDR_MASK	0x3ffff
+ #define PRU0_IRAM_ADDR_MASK	0x34000
+ #define PRU1_IRAM_ADDR_MASK	0x38000
++#define RTU0_IRAM_ADDR_MASK	0x4000
++#define RTU1_IRAM_ADDR_MASK	0x6000
++#define TX_PRU0_IRAM_ADDR_MASK	0xa000
++#define TX_PRU1_IRAM_ADDR_MASK	0xc000
+ 
+ /* PRU device addresses for various type of PRU RAMs */
+ #define PRU_IRAM_DA	0	/* Instruction RAM */
+@@ -74,12 +78,38 @@ enum pru_iomem {
+ 	PRU_IOMEM_MAX,
+ };
+ 
++/**
++ * enum pru_type - PRU core type identifier
++ *
++ * @PRU_TYPE_PRU: Programmable Real-time Unit
++ * @PRU_TYPE_RTU: Auxiliary Programmable Real-Time Unit
++ * @PRU_TYPE_TX_PRU: Transmit Programmable Real-Time Unit
++ * @PRU_TYPE_MAX: just keep this one at the end
++ */
++enum pru_type {
++	PRU_TYPE_PRU = 0,
++	PRU_TYPE_RTU,
++	PRU_TYPE_TX_PRU,
++	PRU_TYPE_MAX,
++};
++
++/**
++ * struct pru_private_data - device data for a PRU core
++ * @type: type of the PRU core (PRU, RTU, Tx_PRU)
++ * @is_k3: flag used to identify the need for special load handling
++ */
++struct pru_private_data {
++	enum pru_type type;
++	unsigned int is_k3 : 1;
++};
++
+ /**
+  * struct pru_rproc - PRU remoteproc structure
+  * @id: id of the PRU core within the PRUSS
+  * @dev: PRU core device pointer
+  * @pruss: back-reference to parent PRUSS structure
+  * @rproc: remoteproc pointer for this PRU core
++ * @data: PRU core specific data
+  * @mem_regions: data for each of the PRU memory regions
+  * @fw_name: name of firmware image used during loading
+  * @mapped_irq: virtual interrupt numbers of created fw specific mapping
+@@ -94,6 +124,7 @@ struct pru_rproc {
+ 	struct device *dev;
+ 	struct pruss *pruss;
+ 	struct rproc *rproc;
++	const struct pru_private_data *data;
+ 	struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
+ 	const char *fw_name;
+ 	unsigned int *mapped_irq;
+@@ -319,11 +350,12 @@ static int pru_rproc_start(struct rproc *rproc)
+ {
+ 	struct device *dev = &rproc->dev;
+ 	struct pru_rproc *pru = rproc->priv;
++	const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" };
+ 	u32 val;
+ 	int ret;
+ 
+-	dev_dbg(dev, "starting PRU%d: entry-point = 0x%llx\n",
+-		pru->id, (rproc->bootaddr >> 2));
++	dev_dbg(dev, "starting %s%d: entry-point = 0x%llx\n",
++		names[pru->data->type], pru->id, (rproc->bootaddr >> 2));
+ 
+ 	ret = pru_handle_intrmap(rproc);
+ 	/*
+@@ -345,9 +377,10 @@ static int pru_rproc_stop(struct rproc *rproc)
+ {
+ 	struct device *dev = &rproc->dev;
+ 	struct pru_rproc *pru = rproc->priv;
++	const char *names[PRU_TYPE_MAX] = { "PRU", "RTU", "Tx_PRU" };
+ 	u32 val;
+ 
+-	dev_dbg(dev, "stopping PRU%d\n", pru->id);
++	dev_dbg(dev, "stopping %s%d\n", names[pru->data->type], pru->id);
+ 
+ 	val = pru_control_read_reg(pru, PRU_CTRL_CTRL);
+ 	val &= ~CTRL_CTRL_EN;
+@@ -459,9 +492,52 @@ static struct rproc_ops pru_rproc_ops = {
+ 	.da_to_va	= pru_rproc_da_to_va,
+ };
+ 
++/*
++ * Custom memory copy implementation for ICSSG PRU/RTU/Tx_PRU Cores
++ *
++ * The ICSSG PRU/RTU/Tx_PRU cores have a memory copying issue with IRAM
++ * memories, that is not seen on previous generation SoCs. The data is reflected
++ * properly in the IRAM memories only for integer (4-byte) copies. Any unaligned
++ * copies result in all the other pre-existing bytes zeroed out within that
++ * 4-byte boundary, thereby resulting in wrong text/code in the IRAMs. Also, the
++ * IRAM memory port interface does not allow any 8-byte copies (as commonly used
++ * by ARM64 memcpy implementation) and throws an exception. The DRAM memory
++ * ports do not show this behavior.
++ */
++static int pru_rproc_memcpy(void *dest, const void *src, size_t count)
++{
++	const u32 *s = src;
++	u32 *d = dest;
++	size_t size = count / 4;
++	u32 *tmp_src = NULL;
++
++	/*
++	 * TODO: relax limitation of 4-byte aligned dest addresses and copy
++	 * sizes
++	 */
++	if ((long)dest % 4 || count % 4)
++		return -EINVAL;
++
++	/* src offsets in ELF firmware image can be non-aligned */
++	if ((long)src % 4) {
++		tmp_src = kmemdup(src, count, GFP_KERNEL);
++		if (!tmp_src)
++			return -ENOMEM;
++		s = tmp_src;
++	}
++
++	while (size--)
++		*d++ = *s++;
++
++	kfree(tmp_src);
++
++	return 0;
++}
++
+ static int
+ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw)
+ {
++	struct pru_rproc *pru = rproc->priv;
+ 	struct device *dev = &rproc->dev;
+ 	struct elf32_hdr *ehdr;
+ 	struct elf32_phdr *phdr;
+@@ -509,7 +585,17 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw)
+ 			break;
+ 		}
+ 
+-		memcpy(ptr, elf_data + phdr->p_offset, filesz);
++		if (pru->data->is_k3 && is_iram) {
++			ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset,
++					       filesz);
++			if (ret) {
++				dev_err(dev, "PRU memory copy failed for da 0x%x memsz 0x%x\n",
++					da, memsz);
++				break;
++			}
++		} else {
++			memcpy(ptr, elf_data + phdr->p_offset, filesz);
++		}
+ 
+ 		/* skip the memzero logic performed by remoteproc ELF loader */
+ 	}
+@@ -615,9 +701,17 @@ static int pru_rproc_set_id(struct pru_rproc *pru)
+ 	int ret = 0;
+ 
+ 	switch (pru->mem_regions[PRU_IOMEM_IRAM].pa & PRU_IRAM_ADDR_MASK) {
++	case TX_PRU0_IRAM_ADDR_MASK:
++		fallthrough;
++	case RTU0_IRAM_ADDR_MASK:
++		fallthrough;
+ 	case PRU0_IRAM_ADDR_MASK:
+ 		pru->id = 0;
+ 		break;
++	case TX_PRU1_IRAM_ADDR_MASK:
++		fallthrough;
++	case RTU1_IRAM_ADDR_MASK:
++		fallthrough;
+ 	case PRU1_IRAM_ADDR_MASK:
+ 		pru->id = 1;
+ 		break;
+@@ -638,8 +732,13 @@ static int pru_rproc_probe(struct platform_device *pdev)
+ 	struct rproc *rproc = NULL;
+ 	struct resource *res;
+ 	int i, ret;
++	const struct pru_private_data *data;
+ 	const char *mem_names[PRU_IOMEM_MAX] = { "iram", "control", "debug" };
+ 
++	data = of_device_get_match_data(&pdev->dev);
++	if (!data)
++		return -ENODEV;
++
+ 	ret = of_property_read_string(np, "firmware-name", &fw_name);
+ 	if (ret) {
+ 		dev_err(dev, "unable to retrieve firmware-name %d\n", ret);
+@@ -672,6 +771,7 @@ static int pru_rproc_probe(struct platform_device *pdev)
+ 
+ 	pru = rproc->priv;
+ 	pru->dev = dev;
++	pru->data = data;
+ 	pru->pruss = platform_get_drvdata(ppdev);
+ 	pru->rproc = rproc;
+ 	pru->fw_name = fw_name;
+@@ -723,11 +823,33 @@ static int pru_rproc_remove(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static const struct pru_private_data pru_data = {
++	.type = PRU_TYPE_PRU,
++};
++
++static const struct pru_private_data k3_pru_data = {
++	.type = PRU_TYPE_PRU,
++	.is_k3 = 1,
++};
++
++static const struct pru_private_data k3_rtu_data = {
++	.type = PRU_TYPE_RTU,
++	.is_k3 = 1,
++};
++
++static const struct pru_private_data k3_tx_pru_data = {
++	.type = PRU_TYPE_TX_PRU,
++	.is_k3 = 1,
++};
++
+ static const struct of_device_id pru_rproc_match[] = {
+-	{ .compatible = "ti,am3356-pru", },
+-	{ .compatible = "ti,am4376-pru", },
+-	{ .compatible = "ti,am5728-pru", },
+-	{ .compatible = "ti,k2g-pru",    },
++	{ .compatible = "ti,am3356-pru",	.data = &pru_data },
++	{ .compatible = "ti,am4376-pru",	.data = &pru_data },
++	{ .compatible = "ti,am5728-pru",	.data = &pru_data },
++	{ .compatible = "ti,k2g-pru",		.data = &pru_data },
++	{ .compatible = "ti,am654-pru",		.data = &k3_pru_data },
++	{ .compatible = "ti,am654-rtu",		.data = &k3_rtu_data },
++	{ .compatible = "ti,am654-tx-pru",	.data = &k3_tx_pru_data },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, pru_rproc_match);

board/PSG/iot2050/files/patches-5.10/0039-remoteproc-pru-Fix-loading-of-GNU-Binutils-ELF.patch

@@ -0,0 +1,49 @@
+From 8bd5f9b960ab37be904871abd5e62d00c29bfcef Mon Sep 17 00:00:00 2001
+From: Dimitar Dimitrov <dimitar@dinux.eu>
+Date: Wed, 30 Dec 2020 12:50:05 +0200
+Subject: [PATCH] remoteproc: pru: Fix loading of GNU Binutils ELF
+
+PRU port of GNU Binutils lacks support for separate address spaces.
+PRU IRAM addresses are marked with artificial offset to differentiate
+them from DRAM addresses. Hence remoteproc must mask IRAM addresses
+coming from GNU ELF in order to get the true hardware address.
+
+PRU firmware used for testing was the example in:
+  https://github.com/dinuxbg/pru-gcc-examples/tree/master/blinking-led/pru
+
+Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
+Link: https://lore.kernel.org/r/20201230105005.30492-1-dimitar@dinux.eu
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 421ebbc1c02d..a113e150d5d5 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -450,6 +450,24 @@ static void *pru_i_da_to_va(struct pru_rproc *pru, u32 da, size_t len)
+ 	if (len == 0)
+ 		return NULL;
+ 
++	/*
++	 * GNU binutils do not support multiple address spaces. The GNU
++	 * linker's default linker script places IRAM at an arbitrary high
++	 * offset, in order to differentiate it from DRAM. Hence we need to
++	 * strip the artificial offset in the IRAM addresses coming from the
++	 * ELF file.
++	 *
++	 * The TI proprietary linker would never set those higher IRAM address
++	 * bits anyway. PRU architecture limits the program counter to 16-bit
++	 * word-address range. This in turn corresponds to 18-bit IRAM
++	 * byte-address range for ELF.
++	 *
++	 * Two more bits are added just in case to make the final 20-bit mask.
++	 * Idea is to have a safeguard in case TI decides to add banking
++	 * in future SoCs.
++	 */
++	da &= 0xfffff;
++
+ 	if (da >= PRU_IRAM_DA &&
+ 	    da + len <= PRU_IRAM_DA + pru->mem_regions[PRU_IOMEM_IRAM].size) {
+ 		offset = da - PRU_IRAM_DA;

board/PSG/iot2050/files/patches-5.10/0040-remoteproc-pru-Fix-firmware-loading-crashes-on-K3-So.patch

@@ -0,0 +1,36 @@
+From 298c53f0a2632c7ec35556d00a914f3b9cfa9708 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Mon, 15 Mar 2021 15:58:59 -0500
+Subject: [PATCH] remoteproc: pru: Fix firmware loading crashes on K3 SoCs
+
+The K3 PRUs are 32-bit processors and in general have some limitations
+in using the standard ARMv8 memcpy function for loading firmware segments,
+so the driver already uses a custom memcpy implementation. This added
+logic however is limited to only IRAMs at the moment, but the loading
+into Data RAMs is not completely ok either and does generate a kernel
+crash for unaligned accesses.
+
+Fix these crashes by removing the existing IRAM logic limitation and
+extending the custom memcpy usage to Data RAMs as well for all K3 SoCs.
+
+Fixes: 1d39f4d19921 ("remoteproc: pru: Add support for various PRU cores on K3 AM65x SoCs")
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Link: https://lore.kernel.org/r/20210315205859.19590-1-s-anna@ti.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index a113e150d5d5..21105592a83d 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -603,7 +603,7 @@ pru_rproc_load_elf_segments(struct rproc *rproc, const struct firmware *fw)
+ 			break;
+ 		}
+ 
+-		if (pru->data->is_k3 && is_iram) {
++		if (pru->data->is_k3) {
+ 			ret = pru_rproc_memcpy(ptr, elf_data + phdr->p_offset,
+ 					       filesz);
+ 			if (ret) {

board/PSG/iot2050/files/patches-5.10/0041-remoteproc-pru-Fixup-interrupt-parent-logic-for-fw-e.patch

@@ -0,0 +1,74 @@
+From c825c3a811080c0f36390ff48910e4b9f5d5e527 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Wed, 7 Apr 2021 10:56:39 -0500
+Subject: [PATCH] remoteproc: pru: Fixup interrupt-parent logic for fw events
+
+The PRU firmware interrupt mapping logic in pru_handle_intrmap() uses
+of_irq_find_parent() with PRU device node to get a handle to the PRUSS
+Interrupt Controller at present. This logic however requires that the
+PRU nodes always define a interrupt-parent property. This property is
+neither a required/defined property as per the PRU remoteproc binding,
+nor is relevant from a DT node point of view without any associated
+interrupts. The current logic finds a wrong interrupt controller and
+fails to perform proper mapping without any interrupt-parent property
+in the PRU nodes.
+
+Fix this logic to always find and use the sibling interrupt controller.
+Also, while at this, fix the acquired interrupt controller device node
+reference properly.
+
+Fixes: c75c9fdac66e ("remoteproc: pru: Add support for PRU specific interrupt configuration")
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Link: https://lore.kernel.org/r/20210407155641.5501-2-s-anna@ti.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 15 ++++++++++++---
+ 1 file changed, 12 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 21105592a83d..773c09d01958 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -284,7 +284,7 @@ static int pru_handle_intrmap(struct rproc *rproc)
+ 	struct pru_rproc *pru = rproc->priv;
+ 	struct pru_irq_rsc *rsc = pru->pru_interrupt_map;
+ 	struct irq_fwspec fwspec;
+-	struct device_node *irq_parent;
++	struct device_node *parent, *irq_parent;
+ 	int i, ret = 0;
+ 
+ 	/* not having pru_interrupt_map is not an error */
+@@ -312,9 +312,16 @@ static int pru_handle_intrmap(struct rproc *rproc)
+ 
+ 	/*
+ 	 * parse and fill in system event to interrupt channel and
+-	 * channel-to-host mapping
++	 * channel-to-host mapping. The interrupt controller to be used
++	 * for these mappings for a given PRU remoteproc is always its
++	 * corresponding sibling PRUSS INTC node.
+ 	 */
+-	irq_parent = of_irq_find_parent(pru->dev->of_node);
++	parent = of_get_parent(dev_of_node(pru->dev));
++	if (!parent)
++		return -ENODEV;
++
++	irq_parent = of_get_child_by_name(parent, "interrupt-controller");
++	of_node_put(parent);
+ 	if (!irq_parent) {
+ 		kfree(pru->mapped_irq);
+ 		return -ENODEV;
+@@ -337,11 +344,13 @@ static int pru_handle_intrmap(struct rproc *rproc)
+ 			goto map_fail;
+ 		}
+ 	}
++	of_node_put(irq_parent);
+ 
+ 	return ret;
+ 
+ map_fail:
+ 	pru_dispose_irq_mapping(pru);
++	of_node_put(irq_parent);
+ 
+ 	return ret;
+ }

board/PSG/iot2050/files/patches-5.10/0042-remoteproc-pru-Fix-wrong-success-return-value-for-fw.patch

@@ -0,0 +1,41 @@
+From f7a7510e74747eab9f009a9e1f67cb076d044ce4 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Wed, 7 Apr 2021 10:56:40 -0500
+Subject: [PATCH] remoteproc: pru: Fix wrong success return value for fw events
+
+The irq_create_fwspec_mapping() returns a proper virq value on success
+and 0 upon any failure. The pru_handle_intrmap() treats this as an error
+and disposes all firmware event mappings correctly, but is returning
+this incorrect value as is, letting the pru_rproc_start() interpret it
+as a success and boot the PRU.
+
+Fix this by returning an error value back upon any such failure. While
+at this, revise the error trace to print some meaningful info about the
+failed event.
+
+Fixes: c75c9fdac66e ("remoteproc: pru: Add support for PRU specific interrupt configuration")
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Link: https://lore.kernel.org/r/20210407155641.5501-3-s-anna@ti.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 773c09d01958..e0c5fce8bccd 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -339,8 +339,10 @@ static int pru_handle_intrmap(struct rproc *rproc)
+ 
+ 		pru->mapped_irq[i] = irq_create_fwspec_mapping(&fwspec);
+ 		if (!pru->mapped_irq[i]) {
+-			dev_err(dev, "failed to get virq\n");
+-			ret = pru->mapped_irq[i];
++			dev_err(dev, "failed to get virq for fw mapping %d: event %d chnl %d host %d\n",
++				i, fwspec.param[0], fwspec.param[1],
++				fwspec.param[2]);
++			ret = -EINVAL;
+ 			goto map_fail;
+ 		}
+ 	}

board/PSG/iot2050/files/patches-5.10/0043-remoteproc-pru-Fix-and-cleanup-firmware-interrupt-ma.patch

@@ -0,0 +1,96 @@
+From b763cdabc4c54e897400dc3fbfb3f9a795c41a48 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Wed, 7 Apr 2021 10:56:41 -0500
+Subject: [PATCH] remoteproc: pru: Fix and cleanup firmware interrupt mapping
+ logic
+
+The PRU firmware interrupt mappings are configured and unconfigured in
+.start() and .stop() callbacks respectively using the variables 'evt_count'
+and a 'mapped_irq' pointer. These variables are modified only during these
+callbacks but are not re-initialized/reset properly during unwind or
+failure paths. These stale values caused a kernel crash while stopping a
+PRU remoteproc running a different firmware with no events on a subsequent
+run after a previous run that was running a firmware with events.
+
+Fix this crash by ensuring that the evt_count is 0 and the mapped_irq
+pointer is set to NULL in pru_dispose_irq_mapping(). Also, reset these
+variables properly during any failures in the .start() callback. While
+at this, the pru_dispose_irq_mapping() callsites are all made to look
+the same, moving any conditional logic to inside the function.
+
+Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
+Fixes: c75c9fdac66e ("remoteproc: pru: Add support for PRU specific interrupt configuration")
+Reported-by: Vignesh Raghavendra <vigneshr@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Link: https://lore.kernel.org/r/20210407155641.5501-4-s-anna@ti.com
+Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 22 +++++++++++++++++-----
+ 1 file changed, 17 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index e0c5fce8bccd..d8597027a93e 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -266,12 +266,17 @@ static void pru_rproc_create_debug_entries(struct rproc *rproc)
+ 
+ static void pru_dispose_irq_mapping(struct pru_rproc *pru)
+ {
+-	while (pru->evt_count--) {
++	if (!pru->mapped_irq)
++		return;
++
++	while (pru->evt_count) {
++		pru->evt_count--;
+ 		if (pru->mapped_irq[pru->evt_count] > 0)
+ 			irq_dispose_mapping(pru->mapped_irq[pru->evt_count]);
+ 	}
+ 
+ 	kfree(pru->mapped_irq);
++	pru->mapped_irq = NULL;
+ }
+ 
+ /*
+@@ -307,8 +312,10 @@ static int pru_handle_intrmap(struct rproc *rproc)
+ 	pru->evt_count = rsc->num_evts;
+ 	pru->mapped_irq = kcalloc(pru->evt_count, sizeof(unsigned int),
+ 				  GFP_KERNEL);
+-	if (!pru->mapped_irq)
++	if (!pru->mapped_irq) {
++		pru->evt_count = 0;
+ 		return -ENOMEM;
++	}
+ 
+ 	/*
+ 	 * parse and fill in system event to interrupt channel and
+@@ -317,13 +324,19 @@ static int pru_handle_intrmap(struct rproc *rproc)
+ 	 * corresponding sibling PRUSS INTC node.
+ 	 */
+ 	parent = of_get_parent(dev_of_node(pru->dev));
+-	if (!parent)
++	if (!parent) {
++		kfree(pru->mapped_irq);
++		pru->mapped_irq = NULL;
++		pru->evt_count = 0;
+ 		return -ENODEV;
++	}
+ 
+ 	irq_parent = of_get_child_by_name(parent, "interrupt-controller");
+ 	of_node_put(parent);
+ 	if (!irq_parent) {
+ 		kfree(pru->mapped_irq);
++		pru->mapped_irq = NULL;
++		pru->evt_count = 0;
+ 		return -ENODEV;
+ 	}
+ 
+@@ -398,8 +411,7 @@ static int pru_rproc_stop(struct rproc *rproc)
+ 	pru_control_write_reg(pru, PRU_CTRL_CTRL, val);
+ 
+ 	/* dispose irq mapping - new firmware can provide new mapping */
+-	if (pru->mapped_irq)
+-		pru_dispose_irq_mapping(pru);
++	pru_dispose_irq_mapping(pru);
+ 
+ 	return 0;
+ }

board/PSG/iot2050/files/patches-5.10/0044-watchdog-rti_wdt-Fix-calculation-and-evaluation-of-p.patch

@@ -0,0 +1,51 @@
+From 24637c741eee2b5a90bf9de2e49932440a428e95 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Mon, 21 Feb 2022 17:22:38 +0100
+Subject: [PATCH] watchdog: rti_wdt: Fix calculation and evaluation of preset
+ heartbeat
+
+This ensures that the same value is read back as was eventually
+programmed when using seconds as accuracy. Even then, comparing the more
+precise heartbeat_ms against heartbeat in seconds will almost never
+provide a match and will needlessly raise a warning. Fix by comparing
+apples to apples.
+
+Tested in combination with U-Boot as watchdog starter.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Reviewed-by: Guenter Roeck <linux@roeck-us.net>
+Link: https://lore.kernel.org/r/6a4b54ac-9588-e172-c4c7-b91d524a851e@siemens.com
+Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
+---
+ drivers/watchdog/rti_wdt.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c
+index 46c2a4bd9ebe..06f9d0ee1340 100644
+--- a/drivers/watchdog/rti_wdt.c
++++ b/drivers/watchdog/rti_wdt.c
+@@ -255,6 +255,7 @@ static int rti_wdt_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (readl(wdt->base + RTIDWDCTRL) == WDENABLE_KEY) {
++		int preset_heartbeat;
+ 		u32 time_left_ms;
+ 		u64 heartbeat_ms;
+ 		u32 wsize;
+@@ -265,11 +266,12 @@ static int rti_wdt_probe(struct platform_device *pdev)
+ 		heartbeat_ms <<= WDT_PRELOAD_SHIFT;
+ 		heartbeat_ms *= 1000;
+ 		do_div(heartbeat_ms, wdt->freq);
+-		if (heartbeat_ms != heartbeat * 1000)
++		preset_heartbeat = heartbeat_ms + 500;
++		preset_heartbeat /= 1000;
++		if (preset_heartbeat != heartbeat)
+ 			dev_warn(dev, "watchdog already running, ignoring heartbeat config!\n");
+ 
+-		heartbeat = heartbeat_ms;
+-		heartbeat /= 1000;
++		heartbeat = preset_heartbeat;
+ 
+ 		wsize = readl(wdt->base + RTIWWDSIZECTRL);
+ 		ret = rti_wdt_setup_hw_hb(wdd, wsize);

board/PSG/iot2050/files/patches-5.10/0045-arm64-dts-ti-iot2050-Flip-mmc-device-ordering-on-Adv.patch

@@ -0,0 +1,31 @@
+From f4168139b2d9bd547a33af37a7da49e9aaa3579b Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Sun, 26 Sep 2021 14:05:12 +0200
+Subject: [PATCH] arm64: dts: ti: iot2050: Flip mmc device ordering on Advanced
+ devices
+
+This ensures that the SD card will remain mmc0 across Basic and Advanced
+devices, also avoiding surprises for users coming from the downstream
+kernels.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Acked-by: Aswath Govindraju <a-govindraju@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/fe20d6346f119a28e47d129b616682001299cf0e.1632657917.git.jan.kiszka@web.de
+---
+ arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index 1008e9162ba2..6261ca8ee2d8 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -17,6 +17,8 @@
+ / {
+ 	aliases {
+ 		spi0 = &mcu_spi0;
++		mmc0 = &sdhci1;
++		mmc1 = &sdhci0;
+ 	};
+ 
+ 	chosen {

board/PSG/iot2050/files/patches-5.10/0046-arm64-dts-ti-iot2050-Disable-SR2.0-only-PRUs.patch

@@ -0,0 +1,49 @@
+From 6a79802036a60a289f350f16b804345454cba6f2 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Sun, 26 Sep 2021 14:05:13 +0200
+Subject: [PATCH] arm64: dts: ti: iot2050: Disable SR2.0-only PRUs
+
+The IOT2050 devices described so far are using SR1.0 silicon, thus do
+not have the additional PRUs of the ICSSG of the SR2.0. Disable them.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Acked-by: Aswath Govindraju <a-govindraju@ti.com>
+Acked-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/189a91866fb1af02e4fd2345dc56774aa069d5ba.1632657917.git.jan.kiszka@web.de
+---
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index 6261ca8ee2d8..58c8e64d5885 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -716,3 +716,27 @@ &icssg1_mdio {
+ &icssg2_mdio {
+ 	status = "disabled";
+ };
++
++&tx_pru0_0 {
++	status = "disabled";
++};
++
++&tx_pru0_1 {
++	status = "disabled";
++};
++
++&tx_pru1_0 {
++	status = "disabled";
++};
++
++&tx_pru1_1 {
++	status = "disabled";
++};
++
++&tx_pru2_0 {
++	status = "disabled";
++};
++
++&tx_pru2_1 {
++	status = "disabled";
++};

board/PSG/iot2050/files/patches-5.10/0047-arm64-dts-ti-iot2050-Add-enabled-mailboxes-and-carve.patch

@@ -0,0 +1,66 @@
+From b2d1ed865f9b50d3de5b946f7dec0b16770b70c6 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Sun, 26 Sep 2021 14:05:14 +0200
+Subject: [PATCH] arm64: dts: ti: iot2050: Add/enabled mailboxes and carve-outs
+ for R5F cores
+
+Analogously to the am654-base-board, configure the mailboxes for the two
+R5F cores, add them and the already existing memory carve-outs to the
+related MCU nodes. Allows to load applications under Linux onto the
+cores, e.g. the RTI watchdog firmware.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Reviewed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/1776f8be19b39a938d9248fcfc5332b753783c3e.1632657917.git.jan.kiszka@web.de
+---
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 26 +++++++++++++++++--
+ 1 file changed, 24 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index 58c8e64d5885..b29537088289 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -658,11 +658,21 @@ &pcie1_ep {
+ };
+ 
+ &mailbox0_cluster0 {
+-	status = "disabled";
++	interrupts = <436>;
++
++	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
++		ti,mbox-tx = <1 0 0>;
++		ti,mbox-rx = <0 0 0>;
++	};
+ };
+ 
+ &mailbox0_cluster1 {
+-	status = "disabled";
++	interrupts = <432>;
++
++	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
++		ti,mbox-tx = <1 0 0>;
++		ti,mbox-rx = <0 0 0>;
++	};
+ };
+ 
+ &mailbox0_cluster2 {
+@@ -705,6 +715,18 @@ &mailbox0_cluster11 {
+ 	status = "disabled";
+ };
+ 
++&mcu_r5fss0_core0 {
++	memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
++			<&mcu_r5fss0_core0_memory_region>;
++	mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
++};
++
++&mcu_r5fss0_core1 {
++	memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
++			<&mcu_r5fss0_core1_memory_region>;
++	mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
++};
++
+ &icssg0_mdio {
+ 	status = "disabled";
+ };

board/PSG/iot2050/files/patches-5.10/0048-arm64-dts-ti-iot2050-Prepare-for-adding-2nd-generati.patch

@@ -0,0 +1,360 @@
+From 5a787ba2a83e7c3f97b17a3e85feba1194bff3b1 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Sun, 26 Sep 2021 14:05:16 +0200
+Subject: [PATCH] arm64: dts: ti: iot2050: Prepare for adding 2nd-generation
+ boards
+
+The current IOT2050 devices are Product Generation 1 (PG1), using SR1.0
+AM65x silicon. Upcoming PG2 devices will use SR2.x SoCs and will
+therefore need separate device trees. Prepare for that by factoring out
+common bits that will be shared across both generations.
+
+At this chance, drop a link to the product homepage to in the top-level
+dts files. Also fix a typo in my email address in some headers.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/31fece05f9728a852c0632985c4fa537cced4ece.1632657917.git.jan.kiszka@web.de
+---
+ .../dts/ti/k3-am65-iot2050-common-pg1.dtsi    | 46 +++++++++++++++
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 35 +-----------
+ ...ts => k3-am6528-iot2050-basic-common.dtsi} | 12 +---
+ .../boot/dts/ti/k3-am6528-iot2050-basic.dts   | 56 +++----------------
+ ...=> k3-am6548-iot2050-advanced-common.dtsi} |  8 +--
+ .../dts/ti/k3-am6548-iot2050-advanced.dts     | 50 +++--------------
+ 6 files changed, 67 insertions(+), 140 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi
+ copy arch/arm64/boot/dts/ti/{k3-am6528-iot2050-basic.dts => k3-am6528-iot2050-basic-common.dtsi} (80%)
+ copy arch/arm64/boot/dts/ti/{k3-am6548-iot2050-advanced.dts => k3-am6548-iot2050-advanced-common.dtsi} (85%)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi
+new file mode 100644
+index 000000000000..51f902fa35a7
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg1.dtsi
+@@ -0,0 +1,46 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2021
++ *
++ * Authors:
++ *   Jan Kiszka <jan.kiszka@siemens.com>
++ *
++ * Common bits of the IOT2050 Basic and Advanced variants, PG1
++ */
++
++&dss {
++	assigned-clocks = <&k3_clks 67 2>;
++	assigned-clock-parents = <&k3_clks 67 5>;
++};
++
++&serdes0 {
++	status = "disabled";
++};
++
++&sdhci1 {
++	no-1-8-v;
++};
++
++&tx_pru0_0 {
++	status = "disabled";
++};
++
++&tx_pru0_1 {
++	status = "disabled";
++};
++
++&tx_pru1_0 {
++	status = "disabled";
++};
++
++&tx_pru1_1 {
++	status = "disabled";
++};
++
++&tx_pru2_0 {
++	status = "disabled";
++};
++
++&tx_pru2_1 {
++	status = "disabled";
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index b29537088289..65da226847f4 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -4,13 +4,11 @@
+  *
+  * Authors:
+  *   Le Jin <le.jin@siemens.com>
+- *   Jan Kiszka <jan.kiszk@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
+  *
+- * Common bits of the IOT2050 Basic and Advanced variants
++ * Common bits of the IOT2050 Basic and Advanced variants, PG1 and PG2
+  */
+ 
+-/dts-v1/;
+-
+ #include "k3-am654.dtsi"
+ #include <dt-bindings/phy/phy.h>
+ 
+@@ -557,7 +555,6 @@ &sdhci1 {
+ 	pinctrl-0 = <&main_mmc1_pins_default>;
+ 	ti,driver-strength-ohm = <50>;
+ 	disable-wp;
+-	no-1-8-v;
+ };
+ 
+ &usb0 {
+@@ -631,10 +628,6 @@ dpi_out: endpoint {
+ 	};
+ };
+ 
+-&serdes0 {
+-	status = "disabled";
+-};
+-
+ &pcie0_rc {
+ 	status = "disabled";
+ };
+@@ -738,27 +731,3 @@ &icssg1_mdio {
+ &icssg2_mdio {
+ 	status = "disabled";
+ };
+-
+-&tx_pru0_0 {
+-	status = "disabled";
+-};
+-
+-&tx_pru0_1 {
+-	status = "disabled";
+-};
+-
+-&tx_pru1_0 {
+-	status = "disabled";
+-};
+-
+-&tx_pru1_1 {
+-	status = "disabled";
+-};
+-
+-&tx_pru2_0 {
+-	status = "disabled";
+-};
+-
+-&tx_pru2_1 {
+-	status = "disabled";
+-};
+diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
+similarity index 80%
+copy from arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+copy to arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
+index 94bb5dd39122..4a9bf7d7c07d 100644
+--- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
++++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
+@@ -4,20 +4,14 @@
+  *
+  * Authors:
+  *   Le Jin <le.jin@siemens.com>
+- *   Jan Kiszka <jan.kiszk@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
+  *
+- * AM6528-based (dual-core) IOT2050 Basic variant
+- * 1 GB RAM, no eMMC, main_uart0 on connector X30
++ * Common bits of the IOT2050 Basic variant, PG1 and PG2
+  */
+ 
+-/dts-v1/;
+-
+ #include "k3-am65-iot2050-common.dtsi"
+ 
+ / {
+-	compatible = "siemens,iot2050-basic", "ti,am654";
+-	model = "SIMATIC IOT2050 Basic";
+-
+ 	memory@80000000 {
+ 		device_type = "memory";
+ 		/* 1G RAM */
+@@ -61,6 +55,6 @@ &main_uart0 {
+ };
+ 
+ &mcu_r5fss0 {
+-	/* lock-step mode not supported on this board */
++	/* lock-step mode not supported on Basic boards */
+ 	ti,cluster-mode = <0>;
+ };
+diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+index 94bb5dd39122..87928ff28214 100644
+--- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
++++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic.dts
+@@ -4,63 +4,21 @@
+  *
+  * Authors:
+  *   Le Jin <le.jin@siemens.com>
+- *   Jan Kiszka <jan.kiszk@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
+  *
+- * AM6528-based (dual-core) IOT2050 Basic variant
++ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 1
+  * 1 GB RAM, no eMMC, main_uart0 on connector X30
++ *
++ * Product homepage:
++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+  */
+ 
+ /dts-v1/;
+ 
+-#include "k3-am65-iot2050-common.dtsi"
++#include "k3-am6528-iot2050-basic-common.dtsi"
++#include "k3-am65-iot2050-common-pg1.dtsi"
+ 
+ / {
+ 	compatible = "siemens,iot2050-basic", "ti,am654";
+ 	model = "SIMATIC IOT2050 Basic";
+-
+-	memory@80000000 {
+-		device_type = "memory";
+-		/* 1G RAM */
+-		reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
+-	};
+-
+-	cpus {
+-		cpu-map {
+-			/delete-node/ cluster1;
+-		};
+-		/delete-node/ cpu@100;
+-		/delete-node/ cpu@101;
+-	};
+-
+-	/delete-node/ l2-cache1;
+-};
+-
+-/* eMMC */
+-&sdhci0 {
+-	status = "disabled";
+-};
+-
+-&main_pmx0 {
+-	main_uart0_pins_default: main-uart0-pins-default {
+-		pinctrl-single,pins = <
+-			AM65X_IOPAD(0x01e4, PIN_INPUT,  0)  /* (AF11) UART0_RXD */
+-			AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0)  /* (AE11) UART0_TXD */
+-			AM65X_IOPAD(0x01ec, PIN_INPUT,  0)  /* (AG11) UART0_CTSn */
+-			AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0)  /* (AD11) UART0_RTSn */
+-			AM65X_IOPAD(0x0188, PIN_INPUT,  1)  /* (D25) UART0_DCDn */
+-			AM65X_IOPAD(0x018c, PIN_INPUT,  1)  /* (B26) UART0_DSRn */
+-			AM65X_IOPAD(0x0190, PIN_OUTPUT, 1)  /* (A24) UART0_DTRn */
+-			AM65X_IOPAD(0x0194, PIN_INPUT,  1)  /* (E24) UART0_RIN */
+-		>;
+-	};
+-};
+-
+-&main_uart0 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&main_uart0_pins_default>;
+-};
+-
+-&mcu_r5fss0 {
+-	/* lock-step mode not supported on this board */
+-	ti,cluster-mode = <0>;
+ };
+diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
+similarity index 85%
+copy from arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
+copy to arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
+index ec9617c13cdb..d25e8b26187f 100644
+--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
++++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
+@@ -4,10 +4,9 @@
+  *
+  * Authors:
+  *   Le Jin <le.jin@siemens.com>
+- *   Jan Kiszka <jan.kiszk@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
+  *
+- * AM6548-based (quad-core) IOT2050 Advanced variant
+- * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
++ * Common bits of the IOT2050 Advanced variant, PG1 and PG2
+  */
+ 
+ /dts-v1/;
+@@ -15,9 +14,6 @@
+ #include "k3-am65-iot2050-common.dtsi"
+ 
+ / {
+-	compatible = "siemens,iot2050-advanced", "ti,am654";
+-	model = "SIMATIC IOT2050 Advanced";
+-
+ 	memory@80000000 {
+ 		device_type = "memory";
+ 		/* 2G RAM */
+diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
+index ec9617c13cdb..077f165bdc68 100644
+--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
++++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced.dts
+@@ -4,57 +4,21 @@
+  *
+  * Authors:
+  *   Le Jin <le.jin@siemens.com>
+- *   Jan Kiszka <jan.kiszk@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
+  *
+- * AM6548-based (quad-core) IOT2050 Advanced variant
++ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 1
+  * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
++ *
++ * Product homepage:
++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
+  */
+ 
+ /dts-v1/;
+ 
+-#include "k3-am65-iot2050-common.dtsi"
++#include "k3-am6548-iot2050-advanced-common.dtsi"
++#include "k3-am65-iot2050-common-pg1.dtsi"
+ 
+ / {
+ 	compatible = "siemens,iot2050-advanced", "ti,am654";
+ 	model = "SIMATIC IOT2050 Advanced";
+-
+-	memory@80000000 {
+-		device_type = "memory";
+-		/* 2G RAM */
+-		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+-	};
+-};
+-
+-&main_pmx0 {
+-	main_mmc0_pins_default: main-mmc0-pins-default {
+-		pinctrl-single,pins = <
+-			AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)  /* (B25) MMC0_CLK */
+-			AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP,   0)  /* (B27) MMC0_CMD */
+-			AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP,   0)  /* (A26) MMC0_DAT0 */
+-			AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP,   0)  /* (E25) MMC0_DAT1 */
+-			AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP,   0)  /* (C26) MMC0_DAT2 */
+-			AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP,   0)  /* (A25) MMC0_DAT3 */
+-			AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP,   0)  /* (E24) MMC0_DAT4 */
+-			AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP,   0)  /* (A24) MMC0_DAT5 */
+-			AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP,   0)  /* (B26) MMC0_DAT6 */
+-			AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP,   0)  /* (D25) MMC0_DAT7 */
+-			AM65X_IOPAD(0x01b8, PIN_OUTPUT_PULLUP,  7)  /* (B23) MMC0_SDWP */
+-			AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP,   0)  /* (A23) MMC0_SDCD */
+-			AM65X_IOPAD(0x01b0, PIN_INPUT,          0)  /* (C25) MMC0_DS */
+-		>;
+-	};
+-};
+-
+-/* eMMC */
+-&sdhci0 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&main_mmc0_pins_default>;
+-	bus-width = <8>;
+-	non-removable;
+-	ti,driver-strength-ohm = <50>;
+-	disable-wp;
+-};
+-
+-&main_uart0 {
+-	status = "disabled";
+ };

board/PSG/iot2050/files/patches-5.10/0049-arm64-dts-ti-iot2050-Add-support-for-product-generat.patch

@@ -0,0 +1,161 @@
+From 4ac8403a21d9ae4deeb0872133ad15243babff98 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Sun, 26 Sep 2021 14:05:17 +0200
+Subject: [PATCH] arm64: dts: ti: iot2050: Add support for product generation 2
+ boards
+
+This adds the devices trees for IOT2050 Product Generation 2 (PG2)
+boards. We have Basic and an Advanced variants again, differing in
+number of cores, RAM size, availability of eMMC and further details.
+The major difference to PG1 is the used silicon revision (SR2.x on
+PG2).
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+Signed-off-by: Nishanth Menon <nm@ti.com>
+Link: https://lore.kernel.org/r/cc868da8264324bde2c87d0c01d4763e3678c706.1632657917.git.jan.kiszka@web.de
+---
+ arch/arm64/boot/dts/ti/Makefile               |  2 +
+ .../dts/ti/k3-am65-iot2050-common-pg2.dtsi    | 51 +++++++++++++++++++
+ .../dts/ti/k3-am6528-iot2050-basic-pg2.dts    | 24 +++++++++
+ .../dts/ti/k3-am6548-iot2050-advanced-pg2.dts | 29 +++++++++++
+ 4 files changed, 106 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts
+ create mode 100644 arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts
+
+diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
+index 22108491f16e..e8a07d411627 100644
+--- a/arch/arm64/boot/dts/ti/Makefile
++++ b/arch/arm64/boot/dts/ti/Makefile
+@@ -8,7 +8,9 @@
+ 
+ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
+ dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic.dtb
++dtb-$(CONFIG_ARCH_K3) += k3-am6528-iot2050-basic-pg2.dtb
+ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
++dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
+ 
+ dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+ 
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
+new file mode 100644
+index 000000000000..e73458ca6900
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi
+@@ -0,0 +1,51 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2021
++ *
++ * Authors:
++ *   Chao Zeng <chao.zeng@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
++ *
++ * Common bits of the IOT2050 Basic and Advanced variants, PG2
++ */
++
++&main_pmx0 {
++	cp2102n_reset_pin_default: cp2102n-reset-pin-default {
++		pinctrl-single,pins = <
++			/* (AF12) GPIO1_24, used as cp2102 reset */
++			AM65X_IOPAD(0x01e0, PIN_OUTPUT, 7)
++		>;
++	};
++};
++
++&main_gpio1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&cp2102n_reset_pin_default>;
++	gpio-line-names =
++		"", "", "", "", "", "", "", "", "", "",
++		"", "", "", "", "", "", "", "", "", "",
++		"", "", "", "", "CP2102N-RESET";
++};
++
++&dss {
++	/* Workaround needed to get DP clock of 154Mhz */
++	assigned-clocks = <&k3_clks 67 0>;
++};
++
++&serdes0 {
++	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
++	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;
++};
++
++&dwc3_0 {
++	assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
++				 <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */
++	phys = <&serdes0 PHY_TYPE_USB3 0>;
++	phy-names = "usb3-phy";
++};
++
++&usb0 {
++	maximum-speed = "super-speed";
++	snps,dis-u1-entry-quirk;
++	snps,dis-u2-entry-quirk;
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts
+new file mode 100644
+index 000000000000..c62549a4b436
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2018-2021
++ *
++ * Authors:
++ *   Le Jin <le.jin@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
++ *
++ * AM6528-based (dual-core) IOT2050 Basic variant, Product Generation 2
++ * 1 GB RAM, no eMMC, main_uart0 on connector X30
++ *
++ * Product homepage:
++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
++ */
++
++/dts-v1/;
++
++#include "k3-am6528-iot2050-basic-common.dtsi"
++#include "k3-am65-iot2050-common-pg2.dtsi"
++
++/ {
++	compatible = "siemens,iot2050-basic-pg2", "ti,am654";
++	model = "SIMATIC IOT2050 Basic PG2";
++};
+diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts
+new file mode 100644
+index 000000000000..f00dc86d01b9
+--- /dev/null
++++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts
+@@ -0,0 +1,29 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) Siemens AG, 2018-2021
++ *
++ * Authors:
++ *   Le Jin <le.jin@siemens.com>
++ *   Jan Kiszka <jan.kiszka@siemens.com>
++ *
++ * AM6548-based (quad-core) IOT2050 Advanced variant, Product Generation 2
++ * 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30
++ *
++ * Product homepage:
++ * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html
++ */
++
++/dts-v1/;
++
++#include "k3-am6548-iot2050-advanced-common.dtsi"
++#include "k3-am65-iot2050-common-pg2.dtsi"
++
++/ {
++	compatible = "siemens,iot2050-advanced-pg2", "ti,am654";
++	model = "SIMATIC IOT2050 Advanced PG2";
++};
++
++&mcu_r5fss0 {
++	/* lock-step mode not supported on this board */
++	ti,cluster-mode = <0>;
++};

board/PSG/iot2050/files/patches-5.10/0050-arm64-dts-ti-iot2050-Add-layout-of-OSPI-flash.patch

@@ -0,0 +1,73 @@
+From bbf4c000baf85a6de349fad3b6a5474a9f9a0af5 Mon Sep 17 00:00:00 2001
+From: Jan Kiszka <jan.kiszka@siemens.com>
+Date: Mon, 21 Mar 2022 15:53:15 +0100
+Subject: [PATCH] arm64: dts: ti: iot2050: Add layout of OSPI flash
+
+Describe the layout of the OSPI flash as the latest firmware uses it.
+Specifically the location of the U-Boot envs is important for userspace
+in order to access it.
+
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+---
+ .../boot/dts/ti/k3-am65-iot2050-common.dtsi   | 48 ++++++++++++++++++-
+ 1 file changed, 46 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+index 65da226847f4..d8661096f2de 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+@@ -603,8 +603,52 @@ flash@0 {
+ 		cdns,tchsh-ns = <60>;
+ 		cdns,tslch-ns = <60>;
+ 		cdns,read-delay = <2>;
+-		#address-cells = <1>;
+-		#size-cells = <1>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			seboot@0 {
++				label = "seboot";
++				reg = <0x0 0x180000>; /* 1.5M */
++			};
++
++			tispl@180000 {
++				label = "tispl";
++				reg = <0x180000 0x200000>; /* 2M */
++			};
++
++			u-boot@380000 {
++				label = "u-boot";
++				reg = <0x380000 0x300000>; /* 3M */
++			};
++
++			env@680000 {
++				label = "env";
++				reg = <0x680000 0x20000>; /* 128K */
++			};
++
++			env-backup@6a0000 {
++				label = "env.backup";
++				reg = <0x6a0000 0x20000>; /* 128K */
++			};
++
++			otpcmd@6c0000 {
++				label = "otpcmd";
++				reg = <0x6c0000 0x10000>; /* 64K */
++			};
++
++			unused@6d0000 {
++				label = "unused";
++				reg = <0x6d0000 0x7b0000>; /* 7872K */
++			};
++
++			seboot-backup@e80000 {
++				label = "seboot.backup";
++				reg = <0xe80000 0x180000>; /* 1.5M */
++			};
++		};
+ 	};
+ };
+ 

board/PSG/iot2050/files/patches-5.10/0051-arm64-dts-ti-k3-am65-main-fix-DSS-irq-trigger-type.patch

@@ -0,0 +1,35 @@
+From bb451cb41a623548fbe16aaef59d4145f6138d4b Mon Sep 17 00:00:00 2001
+From: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Date: Mon, 31 May 2021 16:31:35 +0530
+Subject: [PATCH] arm64: dts: ti: k3-am65-main: fix DSS irq trigger type
+
+DSS irq trigger type is set to IRQ_TYPE_EDGE_RISING. For some reason this
+results in double the amount of expected interrupts, e.g. for normal
+page flipping test the number of interrupts per second is 2 * fps. It is
+as if the IRQ would trigger on both edges.
+
+In any case, it's better to use IRQ_TYPE_LEVEL_HIGH, like the other
+devices do, which seems to fix this problem.
+
+Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
+Signed-off-by: Jyri Sarha <jsarha@ti.com>
+Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+Tested-by: Praneeth Bajjuri <praneeth@ti.com>
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index a506a24bd9c2..dd1e475f2c18 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -861,7 +861,7 @@ dss: dss@4a00000 {
+ 		assigned-clocks = <&k3_clks 67 2>;
+ 		assigned-clock-parents = <&k3_clks 67 5>;
+ 
+-		interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
++		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ 
+ 		dma-coherent;
+ 

board/PSG/iot2050/files/patches-5.10/0052-irqdomain-Export-of_phandle_args_to_fwspec.patch

@@ -0,0 +1,56 @@
+From 8918fc6f1819f4d1760601ec44c7a197f7a8b760 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Tue, 30 Mar 2021 17:24:46 +0530
+Subject: [PATCH] irqdomain: Export of_phandle_args_to_fwspec()
+
+Export of_phandle_args_to_fwspec() to be used by drivers.
+of_phandle_args_to_fwspec() can be used by drivers to get irq specifier
+from device node useful while creating hierarchy domain. This was
+suggested by Marc Zyngier [1].
+
+[1] -> http://lore.kernel.org/r/20190223121143.14c1f150@why.wild-wind.fr.eu.org/
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+---
+ include/linux/irqdomain.h | 2 ++
+ kernel/irq/irqdomain.c    | 6 +++---
+ 2 files changed, 5 insertions(+), 3 deletions(-)
+
+diff --git a/include/linux/irqdomain.h b/include/linux/irqdomain.h
+index ea5a337e0f8b..e653708f59ba 100644
+--- a/include/linux/irqdomain.h
++++ b/include/linux/irqdomain.h
+@@ -387,6 +387,8 @@ extern void irq_domain_disassociate(struct irq_domain *domain,
+ extern unsigned int irq_create_mapping_affinity(struct irq_domain *host,
+ 				      irq_hw_number_t hwirq,
+ 				      const struct irq_affinity_desc *affinity);
++void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, unsigned int count,
++			       struct irq_fwspec *fwspec);
+ extern unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec);
+ extern void irq_dispose_mapping(unsigned int virq);
+ 
+diff --git a/kernel/irq/irqdomain.c b/kernel/irq/irqdomain.c
+index c6b419db68ef..a17e4ce3811d 100644
+--- a/kernel/irq/irqdomain.c
++++ b/kernel/irq/irqdomain.c
+@@ -734,9 +734,8 @@ static int irq_domain_translate(struct irq_domain *d,
+ 	return 0;
+ }
+ 
+-static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args,
+-				      unsigned int count,
+-				      struct irq_fwspec *fwspec)
++void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args, unsigned int count,
++			       struct irq_fwspec *fwspec)
+ {
+ 	int i;
+ 
+@@ -746,6 +745,7 @@ static void of_phandle_args_to_fwspec(struct device_node *np, const u32 *args,
+ 	for (i = 0; i < count; i++)
+ 		fwspec->param[i] = args[i];
+ }
++EXPORT_SYMBOL_GPL(of_phandle_args_to_fwspec);
+ 
+ unsigned int irq_create_fwspec_mapping(struct irq_fwspec *fwspec)
+ {

board/PSG/iot2050/files/patches-5.10/0053-PCI-keystone-Convert-to-using-hierarchy-domain-for-l.patch

@@ -0,0 +1,319 @@
+From 35fc29603cd1d8ceee3ae054528f748d96ace70b Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Tue, 30 Mar 2021 17:24:47 +0530
+Subject: [PATCH] PCI: keystone: Convert to using hierarchy domain for legacy
+ interrupts
+
+K2G provides separate IRQ lines for each of the four legacy interrupts.
+Model this using hierarchy domain instead of linear domain with chained
+IRQ handler.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+---
+ drivers/pci/controller/dwc/pci-keystone.c | 214 ++++++++++++----------
+ 1 file changed, 120 insertions(+), 94 deletions(-)
+
+diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
+index 90482d5246ff..0493e43ba416 100644
+--- a/drivers/pci/controller/dwc/pci-keystone.c
++++ b/drivers/pci/controller/dwc/pci-keystone.c
+@@ -69,6 +69,7 @@
+ 
+ #define IRQ_STATUS(n)			(0x184 + ((n) << 4))
+ #define IRQ_ENABLE_SET(n)		(0x188 + ((n) << 4))
++#define IRQ_ENABLE_CLR(n)		(0x18c + ((n) << 4))
+ #define INTx_EN				BIT(0)
+ 
+ #define ERR_IRQ_STATUS			0x1c4
+@@ -116,7 +117,6 @@ struct keystone_pcie {
+ 	struct dw_pcie		*pci;
+ 	/* PCI Device ID */
+ 	u32			device_id;
+-	int			legacy_host_irqs[PCI_NUM_INTX];
+ 	struct			device_node *legacy_intc_np;
+ 
+ 	int			msi_host_irq;
+@@ -124,7 +124,6 @@ struct keystone_pcie {
+ 	struct phy		**phy;
+ 	struct device_link	**link;
+ 	struct			device_node *msi_intc_np;
+-	struct irq_domain	*legacy_irq_domain;
+ 	struct device_node	*np;
+ 
+ 	/* Application register space */
+@@ -252,26 +251,6 @@ static int ks_pcie_msi_host_init(struct pcie_port *pp)
+ 	return dw_pcie_allocate_domains(pp);
+ }
+ 
+-static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie,
+-				      int offset)
+-{
+-	struct dw_pcie *pci = ks_pcie->pci;
+-	struct device *dev = pci->dev;
+-	u32 pending;
+-	int virq;
+-
+-	pending = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(offset));
+-
+-	if (BIT(0) & pending) {
+-		virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, offset);
+-		dev_dbg(dev, ": irq: irq_offset %d, virq %d\n", offset, virq);
+-		generic_handle_irq(virq);
+-	}
+-
+-	/* EOI the INTx interrupt */
+-	ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset);
+-}
+-
+ /*
+  * Dummy function so that DW core doesn't configure MSI
+  */
+@@ -317,39 +296,120 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
+ 	return IRQ_HANDLED;
+ }
+ 
+-static void ks_pcie_ack_legacy_irq(struct irq_data *d)
++void ks_pcie_irq_eoi(struct irq_data *data)
+ {
++	struct keystone_pcie *ks_pcie = irq_data_get_irq_chip_data(data);
++	irq_hw_number_t hwirq = data->hwirq;
++
++	ks_pcie_app_writel(ks_pcie, IRQ_EOI, hwirq);
++	irq_chip_eoi_parent(data);
+ }
+ 
+-static void ks_pcie_mask_legacy_irq(struct irq_data *d)
++void ks_pcie_irq_enable(struct irq_data *data)
+ {
++	struct keystone_pcie *ks_pcie = irq_data_get_irq_chip_data(data);
++	irq_hw_number_t hwirq = data->hwirq;
++
++	ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(hwirq), INTx_EN);
++	irq_chip_enable_parent(data);
+ }
+ 
+-static void ks_pcie_unmask_legacy_irq(struct irq_data *d)
++void ks_pcie_irq_disable(struct irq_data *data)
+ {
++	struct keystone_pcie *ks_pcie = irq_data_get_irq_chip_data(data);
++	irq_hw_number_t hwirq = data->hwirq;
++
++	ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_CLR(hwirq), INTx_EN);
++	irq_chip_disable_parent(data);
+ }
+ 
+ static struct irq_chip ks_pcie_legacy_irq_chip = {
+-	.name = "Keystone-PCI-Legacy-IRQ",
+-	.irq_ack = ks_pcie_ack_legacy_irq,
+-	.irq_mask = ks_pcie_mask_legacy_irq,
+-	.irq_unmask = ks_pcie_unmask_legacy_irq,
++	.name			= "Keystone-PCI-Legacy-IRQ",
++	.irq_enable		= ks_pcie_irq_enable,
++	.irq_disable		= ks_pcie_irq_disable,
++	.irq_eoi		= ks_pcie_irq_eoi,
++	.irq_mask		= irq_chip_mask_parent,
++	.irq_unmask		= irq_chip_unmask_parent,
++	.irq_retrigger		= irq_chip_retrigger_hierarchy,
++	.irq_set_type		= irq_chip_set_type_parent,
++	.irq_set_affinity	= irq_chip_set_affinity_parent,
+ };
+ 
+-static int ks_pcie_init_legacy_irq_map(struct irq_domain *d,
+-				       unsigned int irq,
+-				       irq_hw_number_t hw_irq)
++static int ks_pcie_legacy_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
++					   unsigned int nr_irqs, void *data)
+ {
+-	irq_set_chip_and_handler(irq, &ks_pcie_legacy_irq_chip,
+-				 handle_level_irq);
+-	irq_set_chip_data(irq, d->host_data);
++	struct keystone_pcie *ks_pcie = domain->host_data;
++	struct device_node *np = ks_pcie->legacy_intc_np;
++	struct irq_fwspec parent_fwspec, *fwspec = data;
++	struct of_phandle_args out_irq;
++	int ret;
++
++	if (nr_irqs != 1)
++		return -EINVAL;
++
++	/*
++	 * Get the correct interrupt from legacy-interrupt-controller node
++	 * corresponding to INTA/INTB/INTC/INTD (passed in fwspec->param[0])
++	 * after performing mapping specified in "interrupt-map".
++	 * interrupt-map = <0 0 0 1 &pcie_intc0 0>, INTA (4th cell in
++	 * interrupt-map) corresponds to 1st entry in "interrupts" (6th cell
++	 * in interrupt-map)
++	 */
++	ret = of_irq_parse_one(np, fwspec->param[0], &out_irq);
++	if (ret < 0) {
++		pr_err("Failed to parse interrupt node\n");
++		return ret;
++	}
++
++	of_phandle_args_to_fwspec(np, out_irq.args, out_irq.args_count, &parent_fwspec);
++
++	ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &parent_fwspec);
++	if (ret < 0) {
++		pr_err("Failed to allocate parent IRQ %u: %d\n",
++		       parent_fwspec.param[0], ret);
++		return ret;
++	}
++
++	ret = irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0],
++					    &ks_pcie_legacy_irq_chip, ks_pcie);
++	if (ret < 0) {
++		pr_err("Failed to set hwirq and chip\n");
++		goto err_set_hwirq_and_chip;
++	}
+ 
+ 	return 0;
++
++err_set_hwirq_and_chip:
++	irq_domain_free_irqs_parent(domain, virq, 1);
++
++	return ret;
++}
++
++static int ks_pcie_irq_domain_translate(struct irq_domain *domain,
++					struct irq_fwspec *fwspec,
++					unsigned long *hwirq,
++					unsigned int *type)
++{
++	if (is_of_node(fwspec->fwnode)) {
++		if (fwspec->param_count != 2)
++			return -EINVAL;
++
++		if (fwspec->param[0] >= PCI_NUM_INTX)
++			return -EINVAL;
++
++		*hwirq = fwspec->param[0];
++		*type = fwspec->param[1];
++
++		return 0;
++	}
++
++	return -EINVAL;
+ }
+ 
+ static const struct irq_domain_ops ks_pcie_legacy_irq_domain_ops = {
+-	.map = ks_pcie_init_legacy_irq_map,
+-	.xlate = irq_domain_xlate_onetwocell,
++	.alloc		= ks_pcie_legacy_irq_domain_alloc,
++	.free		= irq_domain_free_irqs_common,
++	.translate	= ks_pcie_irq_domain_translate,
+ };
+ 
+ /**
+@@ -616,35 +676,6 @@ static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
+ 	chained_irq_exit(chip, desc);
+ }
+ 
+-/**
+- * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
+- * @irq: IRQ line for legacy interrupts
+- * @desc: Pointer to irq descriptor
+- *
+- * Traverse through pending legacy interrupts and invoke handler for each. Also
+- * takes care of interrupt controller level mask/ack operation.
+- */
+-static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
+-{
+-	unsigned int irq = irq_desc_get_irq(desc);
+-	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
+-	struct dw_pcie *pci = ks_pcie->pci;
+-	struct device *dev = pci->dev;
+-	u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
+-	struct irq_chip *chip = irq_desc_get_chip(desc);
+-
+-	dev_dbg(dev, ": Handling legacy irq %d\n", irq);
+-
+-	/*
+-	 * The chained irq handler installation would have replaced normal
+-	 * interrupt driver handler so we need to take care of mask/unmask and
+-	 * ack operation.
+-	 */
+-	chained_irq_enter(chip, desc);
+-	ks_pcie_handle_legacy_irq(ks_pcie, irq_offset);
+-	chained_irq_exit(chip, desc);
+-}
+-
+ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie)
+ {
+ 	struct device *dev = ks_pcie->pci->dev;
+@@ -704,20 +735,33 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)
+ 	struct device *dev = ks_pcie->pci->dev;
+ 	struct irq_domain *legacy_irq_domain;
+ 	struct device_node *np = ks_pcie->np;
++	struct irq_domain *parent_domain;
++	struct device_node *parent_node;
+ 	struct device_node *intc_np;
+-	int irq_count, irq, ret = 0, i;
++	int irq_count, ret = 0;
+ 
+-	intc_np = of_get_child_by_name(np, "legacy-interrupt-controller");
++	intc_np = of_get_child_by_name(np, "interrupt-controller");
+ 	if (!intc_np) {
+-		/*
+-		 * Since legacy interrupts are modeled as edge-interrupts in
+-		 * AM6, keep it disabled for now.
+-		 */
+-		if (ks_pcie->is_am6)
+-			return 0;
+ 		dev_warn(dev, "legacy-interrupt-controller node is absent\n");
+ 		return -EINVAL;
+ 	}
++	ks_pcie->legacy_intc_np = intc_np;
++
++	parent_node = of_irq_find_parent(intc_np);
++	if (!parent_node) {
++		dev_err(dev, "Unable to obtain parent node\n");
++		ret = -ENXIO;
++		goto err;
++	}
++
++	parent_domain = irq_find_host(parent_node);
++	if (!parent_domain) {
++		dev_err(dev, "Unable to obtain parent domain\n");
++		ret = -ENXIO;
++		goto err;
++	}
++
++	of_node_put(parent_node);
+ 
+ 	irq_count = of_irq_count(intc_np);
+ 	if (!irq_count) {
+@@ -726,31 +770,13 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)
+ 		goto err;
+ 	}
+ 
+-	for (i = 0; i < irq_count; i++) {
+-		irq = irq_of_parse_and_map(intc_np, i);
+-		if (!irq) {
+-			ret = -EINVAL;
+-			goto err;
+-		}
+-		ks_pcie->legacy_host_irqs[i] = irq;
+-
+-		irq_set_chained_handler_and_data(irq,
+-						 ks_pcie_legacy_irq_handler,
+-						 ks_pcie);
+-	}
+-
+-	legacy_irq_domain =
+-		irq_domain_add_linear(intc_np, PCI_NUM_INTX,
+-				      &ks_pcie_legacy_irq_domain_ops, NULL);
++	legacy_irq_domain = irq_domain_add_hierarchy(parent_domain, 0, PCI_NUM_INTX, intc_np,
++						     &ks_pcie_legacy_irq_domain_ops, ks_pcie);
+ 	if (!legacy_irq_domain) {
+ 		dev_err(dev, "Failed to add irq domain for legacy irqs\n");
+ 		ret = -EINVAL;
+ 		goto err;
+ 	}
+-	ks_pcie->legacy_irq_domain = legacy_irq_domain;
+-
+-	for (i = 0; i < PCI_NUM_INTX; i++)
+-		ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN);
+ 
+ err:
+ 	of_node_put(intc_np);

board/PSG/iot2050/files/patches-5.10/0054-PCI-keystone-Add-PCI-legacy-interrupt-support-for-AM.patch

@@ -0,0 +1,135 @@
+From 384992832bb4a1b0660bca5f1364b52ddd5bb282 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Tue, 30 Mar 2021 17:24:48 +0530
+Subject: [PATCH] PCI: keystone: Add PCI legacy interrupt support for AM654
+
+Add PCI legacy interrupt support for AM654. AM654 has a single HW
+interrupt line for all the four legacy interrupts INTA/INTB/INTC/INTD.
+The HW interrupt line connected to GIC is a pulse interrupt whereas
+the legacy interrupts by definition is level interrupt. In order to
+provide level interrupt functionality to edge interrupt line, PCIe
+in AM654 has provided IRQ_EOI register. When the SW writes to IRQ_EOI
+register after handling the interrupt, the IP checks the state of
+legacy interrupt and re-triggers pulse interrupt invoking the handler
+again.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+---
+ drivers/pci/controller/dwc/pci-keystone.c | 80 ++++++++++++++++++++++-
+ 1 file changed, 78 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
+index 0493e43ba416..0460ed2a277a 100644
+--- a/drivers/pci/controller/dwc/pci-keystone.c
++++ b/drivers/pci/controller/dwc/pci-keystone.c
+@@ -118,6 +118,7 @@ struct keystone_pcie {
+ 	/* PCI Device ID */
+ 	u32			device_id;
+ 	struct			device_node *legacy_intc_np;
++	struct irq_domain	*legacy_irq_domain;
+ 
+ 	int			msi_host_irq;
+ 	int			num_lanes;
+@@ -296,6 +297,29 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie)
+ 	return IRQ_HANDLED;
+ }
+ 
++static void ks_pcie_am654_legacy_irq_handler(struct irq_desc *desc)
++{
++	struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	int virq, i;
++	u32 reg;
++
++	chained_irq_enter(chip, desc);
++
++	for (i = 0; i < PCI_NUM_INTX; i++) {
++		reg = ks_pcie_app_readl(ks_pcie, IRQ_STATUS(i));
++		if (!(reg & INTx_EN))
++			continue;
++
++		virq = irq_linear_revmap(ks_pcie->legacy_irq_domain, i);
++		generic_handle_irq(virq);
++		ks_pcie_app_writel(ks_pcie, IRQ_STATUS(i), INTx_EN);
++		ks_pcie_app_writel(ks_pcie, IRQ_EOI, i);
++	}
++
++	chained_irq_exit(chip, desc);
++}
++
+ void ks_pcie_irq_eoi(struct irq_data *data)
+ {
+ 	struct keystone_pcie *ks_pcie = irq_data_get_irq_chip_data(data);
+@@ -730,6 +754,54 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie)
+ 	return ret;
+ }
+ 
++static int ks_pcie_am654_intx_map(struct irq_domain *domain, unsigned int irq,
++				  irq_hw_number_t hwirq)
++{
++	irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
++	irq_set_chip_data(irq, domain->host_data);
++
++	return 0;
++}
++
++static const struct irq_domain_ops ks_pcie_am654_irq_domain_ops = {
++	.map = ks_pcie_am654_intx_map,
++};
++
++static int ks_pcie_am654_config_legacy_irq(struct keystone_pcie *ks_pcie)
++{
++	struct device *dev = ks_pcie->pci->dev;
++	struct irq_domain *legacy_irq_domain;
++	struct device_node *np = ks_pcie->np;
++	struct device_node *intc_np;
++	int ret = 0;
++	int irq;
++	int i;
++
++	intc_np = of_get_child_by_name(np, "interrupt-controller");
++	if (!intc_np) {
++		dev_warn(dev, "legacy interrupt-controller node is absent\n");
++		return -EINVAL;
++	}
++
++	irq = irq_of_parse_and_map(intc_np, 0);
++	if (!irq)
++		return -EINVAL;
++
++	irq_set_chained_handler_and_data(irq, ks_pcie_am654_legacy_irq_handler, ks_pcie);
++	legacy_irq_domain = irq_domain_add_linear(intc_np, PCI_NUM_INTX,
++						  &ks_pcie_am654_irq_domain_ops, ks_pcie);
++	if (!legacy_irq_domain) {
++		dev_err(dev, "Failed to add IRQ domain for legacy IRQS\n");
++		return -EINVAL;
++	}
++	ks_pcie->legacy_irq_domain = legacy_irq_domain;
++
++	for (i = 0; i < PCI_NUM_INTX; i++)
++		ks_pcie_app_writel(ks_pcie, IRQ_ENABLE_SET(i), INTx_EN);
++
++	return ret;
++}
++
+ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie)
+ {
+ 	struct device *dev = ks_pcie->pci->dev;
+@@ -837,10 +909,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp)
+ 	int ret;
+ 
+ 	pp->bridge->ops = &ks_pcie_ops;
+-	if (!ks_pcie->is_am6)
++
++	if (!ks_pcie->is_am6) {
+ 		pp->bridge->child_ops = &ks_child_pcie_ops;
++		ret = ks_pcie_config_legacy_irq(ks_pcie);
++	} else {
++		ret = ks_pcie_am654_config_legacy_irq(ks_pcie);
++	}
+ 
+-	ret = ks_pcie_config_legacy_irq(ks_pcie);
+ 	if (ret)
+ 		return ret;
+ 

board/PSG/iot2050/files/patches-5.10/0055-PCI-keystone-Add-workaround-for-Errata-i2037-AM65x-S.patch

@@ -0,0 +1,111 @@
+From a93ffa726f2439e61a683e172dea25bcec02d2a1 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Tue, 30 Mar 2021 17:24:49 +0530
+Subject: [PATCH] PCI: keystone: Add workaround for Errata #i2037 (AM65x SR
+ 1.0)
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Errata #i2037 in AM65x/DRA80xM Processors Silicon Revision 1.0
+(Silicon Errata SPRZ452E–July 2018–Revised June 2020 [1]) mentions
+when an inbound PCIe TLP spans more than two internal AXI 128-byte
+bursts, the bus may corrupt the packet payload and the corrupt data
+may cause associated applications or the processor to hang.
+
+The workaround for Errata #i2037 is to limit the maximum read
+request size and maximum payload size to 128 bytes. Add workaround
+for Errata #i2037 here. The errata and workaround is applicable
+only to AM65x SR 1.0 and later versions of the silicon will have
+this fixed.
+
+[1] -> https://www.ti.com/lit/er/sprz452e/sprz452e.pdf
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+---
+ drivers/pci/controller/dwc/pci-keystone.c | 42 +++++++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
+index 0460ed2a277a..bb7190400ba8 100644
+--- a/drivers/pci/controller/dwc/pci-keystone.c
++++ b/drivers/pci/controller/dwc/pci-keystone.c
+@@ -35,6 +35,11 @@
+ #define PCIE_DEVICEID_SHIFT	16
+ 
+ /* Application registers */
++#define PID				0x000
++#define RTL				GENMASK(15, 11)
++#define RTL_SHIFT			11
++#define AM6_PCI_PG1_RTL_VER		0x15
++
+ #define CMD_STATUS			0x004
+ #define LTSSM_EN_VAL		        BIT(0)
+ #define OB_XLAT_EN_VAL		        BIT(1)
+@@ -106,6 +111,8 @@
+ 
+ #define to_keystone_pcie(x)		dev_get_drvdata((x)->dev)
+ 
++#define PCI_DEVICE_ID_TI_AM654X		0xb00c
++
+ struct ks_pcie_of_data {
+ 	enum dw_pcie_device_mode mode;
+ 	const struct dw_pcie_host_ops *host_ops;
+@@ -621,7 +628,11 @@ static int ks_pcie_start_link(struct dw_pcie *pci)
+ static void ks_pcie_quirk(struct pci_dev *dev)
+ {
+ 	struct pci_bus *bus = dev->bus;
++	struct keystone_pcie *ks_pcie;
++	struct device *bridge_dev;
+ 	struct pci_dev *bridge;
++	u32 val;
++
+ 	static const struct pci_device_id rc_pci_devids[] = {
+ 		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
+ 		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
+@@ -633,6 +644,11 @@ static void ks_pcie_quirk(struct pci_dev *dev)
+ 		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
+ 		{ 0, },
+ 	};
++	static const struct pci_device_id am6_pci_devids[] = {
++		{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654X),
++		 .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
++		{ 0, },
++	};
+ 
+ 	if (pci_is_root_bus(bus))
+ 		bridge = dev;
+@@ -658,6 +674,32 @@ static void ks_pcie_quirk(struct pci_dev *dev)
+ 			pcie_set_readrq(dev, 256);
+ 		}
+ 	}
++
++	/*
++	 * Memory transactions fail with PCI controller in AM654 PG1.0
++	 * when MRRS is set to more than 128 bytes. Force the MRRS to
++	 * 128 Bytes in all downstream devices.
++	 */
++	if (pci_match_id(am6_pci_devids, bridge)) {
++		bridge_dev = pci_get_host_bridge_device(dev);
++		if (!bridge_dev && !bridge_dev->parent)
++			return;
++
++		ks_pcie = dev_get_drvdata(bridge_dev->parent);
++		if (!ks_pcie)
++			return;
++
++		val = ks_pcie_app_readl(ks_pcie, PID);
++		val &= RTL;
++		val >>= RTL_SHIFT;
++		if (val != AM6_PCI_PG1_RTL_VER)
++			return;
++
++		if (pcie_get_readrq(dev) > 128) {
++			dev_info(&dev->dev, "limiting MRRS to 128 bytes\n");
++			pcie_set_readrq(dev, 128);
++		}
++	}
+ }
+ DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk);
+ 

board/PSG/iot2050/files/patches-5.10/0056-arm64-dts-ti-k3-am65-main-Add-properties-to-support-.patch

@@ -0,0 +1,83 @@
+From 6b83032ac7c35ad60f82316cf87264c6e6bc8b83 Mon Sep 17 00:00:00 2001
+From: Kishon Vijay Abraham I <kishon@ti.com>
+Date: Tue, 30 Mar 2021 17:38:07 +0530
+Subject: [PATCH] arm64: dts: ti: k3-am65-main: Add properties to support
+ legacy interrupts
+
+Add DT properties in PCIe DT node to support legacy interrupts.
+
+Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
+Signed-off-by: Sekhar Nori <nsekhar@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+[Jan: rebased over upstream]
+Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
+---
+ arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 34 +++++++++++++++++++++---
+ 1 file changed, 30 insertions(+), 4 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+index dd1e475f2c18..2911b4286c97 100644
+--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
++++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+@@ -700,8 +700,8 @@ pcie0_rc: pcie@5500000 {
+ 		power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
+-			  0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
++		ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000>,
++			 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
+ 		ti,syscon-pcie-id = <&pcie_devid>;
+ 		ti,syscon-pcie-mode = <&pcie0_mode>;
+ 		bus-range = <0x0 0xff>;
+@@ -711,6 +711,19 @@ pcie0_rc: pcie@5500000 {
+ 		interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ 		msi-map = <0x0 &gic_its 0x0 0x10000>;
+ 		device_type = "pci";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie0_intc 0>, /* INT A */
++				<0 0 0 2 &pcie0_intc 0>, /* INT B */
++				<0 0 0 3 &pcie0_intc 0>, /* INT C */
++				<0 0 0 4 &pcie0_intc 0>; /* INT D */
++
++		pcie0_intc: interrupt-controller {
++			interrupt-controller;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic500>;
++			interrupts = <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
++		};
+ 	};
+ 
+ 	pcie0_ep: pcie-ep@5500000 {
+@@ -733,8 +746,8 @@ pcie1_rc: pcie@5600000 {
+ 		power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
+-		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
+-			  0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
++		ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000>,
++			 <0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
+ 		ti,syscon-pcie-id = <&pcie_devid>;
+ 		ti,syscon-pcie-mode = <&pcie1_mode>;
+ 		bus-range = <0x0 0xff>;
+@@ -744,6 +757,19 @@ pcie1_rc: pcie@5600000 {
+ 		interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
+ 		msi-map = <0x0 &gic_its 0x10000 0x10000>;
+ 		device_type = "pci";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
++				<0 0 0 2 &pcie1_intc 0>, /* INT B */
++				<0 0 0 3 &pcie1_intc 0>, /* INT C */
++				<0 0 0 4 &pcie1_intc 0>; /* INT D */
++
++		pcie1_intc: interrupt-controller {
++			interrupt-controller;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic500>;
++			interrupts = <GIC_SPI 343 IRQ_TYPE_EDGE_RISING>;
++		};
+ 	};
+ 
+ 	pcie1_ep: pcie-ep@5600000 {

board/PSG/iot2050/files/patches-5.10/0057-remoteproc-Fix-unbalanced-boot-with-sysfs-for-no-aut.patch

@@ -0,0 +1,74 @@
+From 83bf54e1b9e7e1a1f7e2c37dbacc29cac5a3ace0 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 20 Nov 2020 21:01:54 -0600
+Subject: [PATCH] remoteproc: Fix unbalanced boot with sysfs for no auto-boot
+ rprocs
+
+The remoteproc core performs automatic boot and shutdown of a remote
+processor during rproc_add() and rproc_del() for remote processors
+supporting 'auto-boot'. The remoteproc devices not using 'auto-boot'
+require either a remoteproc client driver or a userspace client to
+use the sysfs 'state' variable to perform the boot and shutdown. The
+in-kernel client drivers hold the corresponding remoteproc driver
+module's reference count when they acquire a rproc handle through
+the rproc_get_by_phandle() API, but there is no such support for
+userspace applications performing the boot through sysfs interface.
+
+The shutdown of a remoteproc upon removing a remoteproc platform
+driver is automatic only with 'auto-boot' and this can cause a
+remoteproc with no auto-boot to stay powered on and never freed
+up if booted using the sysfs interface without a matching stop,
+and when the remoteproc driver module is removed or unbound from
+the device. This will result in a memory leak as well as the
+corresponding remoteproc ida being never deallocated. Fix this
+by holding a module reference count for the remoteproc's driver
+during a sysfs 'start' and releasing it during the sysfs 'stop'
+operation.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Acked-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
+---
+ drivers/remoteproc/remoteproc_sysfs.c | 16 +++++++++++++++-
+ 1 file changed, 15 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/remoteproc/remoteproc_sysfs.c b/drivers/remoteproc/remoteproc_sysfs.c
+index 1dbef895e65e..3b05230641c8 100644
+--- a/drivers/remoteproc/remoteproc_sysfs.c
++++ b/drivers/remoteproc/remoteproc_sysfs.c
+@@ -3,6 +3,7 @@
+  * Remote Processor Framework
+  */
+ 
++#include <linux/module.h>
+ #include <linux/remoteproc.h>
+ #include <linux/slab.h>
+ 
+@@ -199,14 +200,27 @@ static ssize_t state_store(struct device *dev,
+ 		if (rproc->state == RPROC_RUNNING)
+ 			return -EBUSY;
+ 
++		/*
++		 * prevent underlying implementation from being removed
++		 * when remoteproc does not support auto-boot
++		 */
++		if (!rproc->auto_boot &&
++		    !try_module_get(dev->parent->driver->owner))
++			return -EINVAL;
++
+ 		ret = rproc_boot(rproc);
+-		if (ret)
++		if (ret) {
+ 			dev_err(&rproc->dev, "Boot failed: %d\n", ret);
++			if (!rproc->auto_boot)
++				module_put(dev->parent->driver->owner);
++		}
+ 	} else if (sysfs_streq(buf, "stop")) {
+ 		if (rproc->state != RPROC_RUNNING)
+ 			return -EINVAL;
+ 
+ 		rproc_shutdown(rproc);
++		if (!rproc->auto_boot)
++			module_put(dev->parent->driver->owner);
+ 	} else {
+ 		dev_err(&rproc->dev, "Unrecognised option: %s\n", buf);
+ 		ret = -EINVAL;

board/PSG/iot2050/files/patches-5.10/0058-remoteproc-Introduce-deny_sysfs_ops-flag.patch

@@ -0,0 +1,96 @@
+From f073941ffe4ef831c17a2f59165f54f2d8ab2ae1 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 26 Mar 2021 13:05:28 -0500
+Subject: [PATCH] remoteproc: Introduce deny_sysfs_ops flag
+
+The remoteproc framework provides sysfs interfaces for changing the
+firmware name and for starting/stopping a remote processor through
+the sysfs files 'state' and 'firmware'. The 'recovery' and 'coredump'
+sysfs files can also be used similarly to control the error recovery
+state machine and coredump of a remoteproc. These interfaces are
+currently  allowed irrespective of how the remoteprocs were booted
+(like remoteproc self auto-boot, remoteproc client-driven boot etc).
+These interfaces can adversely affect a remoteproc and its clients
+especially when a remoteproc is being controlled by a remoteproc
+client driver(s). Also, not all remoteproc drivers may want to
+support the sysfs interfaces by default.
+
+Add support to deny the sysfs state/firmware/recovery/coredump change
+by introducing a state flag 'deny_sysfs_ops' that the individual
+remoteproc drivers can set based on their usage needs. The default
+behavior is to allow the sysfs operations as before.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+---
+ drivers/remoteproc/remoteproc_sysfs.c | 16 ++++++++++++++++
+ include/linux/remoteproc.h            |  2 ++
+ 2 files changed, 18 insertions(+)
+
+diff --git a/drivers/remoteproc/remoteproc_sysfs.c b/drivers/remoteproc/remoteproc_sysfs.c
+index 3b05230641c8..16f4a3ea0b25 100644
+--- a/drivers/remoteproc/remoteproc_sysfs.c
++++ b/drivers/remoteproc/remoteproc_sysfs.c
+@@ -49,6 +49,10 @@ static ssize_t recovery_store(struct device *dev,
+ {
+ 	struct rproc *rproc = to_rproc(dev);
+ 
++	/* restrict sysfs operations if not allowed by remoteproc drivers */
++	if (rproc->deny_sysfs_ops)
++		return -EPERM;
++
+ 	if (sysfs_streq(buf, "enabled")) {
+ 		/* change the flag and begin the recovery process if needed */
+ 		rproc->recovery_disabled = false;
+@@ -108,6 +112,10 @@ static ssize_t coredump_store(struct device *dev,
+ {
+ 	struct rproc *rproc = to_rproc(dev);
+ 
++	/* restrict sysfs operations if not allowed by remoteproc drivers */
++	if (rproc->deny_sysfs_ops)
++		return -EPERM;
++
+ 	if (rproc->state == RPROC_CRASHED) {
+ 		dev_err(&rproc->dev, "can't change coredump configuration\n");
+ 		return -EBUSY;
+@@ -157,6 +165,10 @@ static ssize_t firmware_store(struct device *dev,
+ 	struct rproc *rproc = to_rproc(dev);
+ 	int err;
+ 
++	/* restrict sysfs operations if not allowed by remoteproc drivers */
++	if (rproc->deny_sysfs_ops)
++		return -EPERM;
++
+ 	err = rproc_set_firmware(rproc, buf);
+ 
+ 	return err ? err : count;
+@@ -196,6 +208,10 @@ static ssize_t state_store(struct device *dev,
+ 	struct rproc *rproc = to_rproc(dev);
+ 	int ret = 0;
+ 
++	/* restrict sysfs operations if not allowed by remoteproc drivers */
++	if (rproc->deny_sysfs_ops)
++		return -EPERM;
++
+ 	if (sysfs_streq(buf, "start")) {
+ 		if (rproc->state == RPROC_RUNNING)
+ 			return -EBUSY;
+diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h
+index e8ac041c64d9..02425aac6100 100644
+--- a/include/linux/remoteproc.h
++++ b/include/linux/remoteproc.h
+@@ -508,6 +508,7 @@ struct rproc_dump_segment {
+  * @has_iommu: flag to indicate if remote processor is behind an MMU
+  * @auto_boot: flag to indicate if remote processor should be auto-started
+  * @autonomous: true if an external entity has booted the remote processor
++ * @deny_sysfs_ops: flag to not permit sysfs store operations
+  * @dump_segments: list of segments in the firmware
+  * @nb_vdev: number of vdev currently handled by rproc
+  * @char_dev: character device of the rproc
+@@ -545,6 +546,7 @@ struct rproc {
+ 	bool has_iommu;
+ 	bool auto_boot;
+ 	bool autonomous;
++	bool deny_sysfs_ops;
+ 	struct list_head dump_segments;
+ 	int nb_vdev;
+ 	u8 elf_class;

board/PSG/iot2050/files/patches-5.10/0059-remoteproc-pru-Add-APIs-to-get-and-put-the-PRU-cores.patch

@@ -0,0 +1,279 @@
+From 478e98f1ae92de7db3ba7ebeac66a58d38067ce9 Mon Sep 17 00:00:00 2001
+From: Tero Kristo <t-kristo@ti.com>
+Date: Fri, 26 Mar 2021 15:32:29 -0500
+Subject: [PATCH] remoteproc: pru: Add APIs to get and put the PRU cores
+
+Add two new APIs, pru_rproc_get() and pru_rproc_put(), to the PRU
+driver to allow client drivers to acquire and release the remoteproc
+device associated with a PRU core. The PRU cores are treated as
+resources with only one client owning it at a time.
+
+The pru_rproc_get() function returns the rproc handle corresponding
+to a PRU core identified by the device tree "ti,prus" property under
+the client node. The pru_rproc_put() is the complementary function
+to pru_rproc_get().
+
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Tero Kristo <t-kristo@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 125 +++++++++++++++++++++++++++++++--
+ include/linux/pruss.h          |  56 +++++++++++++++
+ 2 files changed, 177 insertions(+), 4 deletions(-)
+ create mode 100644 include/linux/pruss.h
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index d8597027a93e..0b57b3f7747f 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -2,7 +2,7 @@
+ /*
+  * PRU-ICSS remoteproc driver for various TI SoCs
+  *
+- * Copyright (C) 2014-2020 Texas Instruments Incorporated - https://www.ti.com/
++ * Copyright (C) 2014-2021 Texas Instruments Incorporated - https://www.ti.com/
+  *
+  * Author(s):
+  *	Suman Anna <s-anna@ti.com>
+@@ -16,6 +16,7 @@
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+ #include <linux/of_irq.h>
++#include <linux/pruss.h>
+ #include <linux/pruss_driver.h>
+ #include <linux/remoteproc.h>
+ 
+@@ -111,6 +112,8 @@ struct pru_private_data {
+  * @rproc: remoteproc pointer for this PRU core
+  * @data: PRU core specific data
+  * @mem_regions: data for each of the PRU memory regions
++ * @client_np: client device node
++ * @lock: mutex to protect client usage
+  * @fw_name: name of firmware image used during loading
+  * @mapped_irq: virtual interrupt numbers of created fw specific mapping
+  * @pru_interrupt_map: pointer to interrupt mapping description (firmware)
+@@ -126,6 +129,8 @@ struct pru_rproc {
+ 	struct rproc *rproc;
+ 	const struct pru_private_data *data;
+ 	struct pruss_mem_region mem_regions[PRU_IOMEM_MAX];
++	struct device_node *client_np;
++	struct mutex lock; /* client access lock */
+ 	const char *fw_name;
+ 	unsigned int *mapped_irq;
+ 	struct pru_irq_rsc *pru_interrupt_map;
+@@ -146,6 +151,117 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
+ 	writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
+ }
+ 
++static struct rproc *__pru_rproc_get(struct device_node *np, int index)
++{
++	struct device_node *rproc_np = NULL;
++	struct platform_device *pdev;
++	struct rproc *rproc;
++
++	rproc_np = of_parse_phandle(np, "ti,prus", index);
++	if (!rproc_np || !of_device_is_available(rproc_np))
++		return ERR_PTR(-ENODEV);
++
++	pdev = of_find_device_by_node(rproc_np);
++	of_node_put(rproc_np);
++
++	if (!pdev)
++		/* probably PRU not yet probed */
++		return ERR_PTR(-EPROBE_DEFER);
++
++	/* make sure it is PRU rproc */
++	if (!is_pru_rproc(&pdev->dev)) {
++		put_device(&pdev->dev);
++		return ERR_PTR(-ENODEV);
++	}
++
++	rproc = platform_get_drvdata(pdev);
++	put_device(&pdev->dev);
++	if (!rproc)
++		return ERR_PTR(-EPROBE_DEFER);
++
++	get_device(&rproc->dev);
++
++	return rproc;
++}
++
++/**
++ * pru_rproc_get() - get the PRU rproc instance from a device node
++ * @np: the user/client device node
++ * @index: index to use for the ti,prus property
++ * @pru_id: optional pointer to return the PRU remoteproc processor id
++ *
++ * This function looks through a client device node's "ti,prus" property at
++ * index @index and returns the rproc handle for a valid PRU remote processor if
++ * found. The function allows only one user to own the PRU rproc resource at a
++ * time. Caller must call pru_rproc_put() when done with using the rproc, not
++ * required if the function returns a failure.
++ *
++ * When optional @pru_id pointer is passed the PRU remoteproc processor id is
++ * returned.
++ *
++ * Return: rproc handle on success, and an ERR_PTR on failure using one
++ * of the following error values
++ *    -ENODEV if device is not found
++ *    -EBUSY if PRU is already acquired by anyone
++ *    -EPROBE_DEFER is PRU device is not probed yet
++ */
++struct rproc *pru_rproc_get(struct device_node *np, int index,
++			    enum pruss_pru_id *pru_id)
++{
++	struct rproc *rproc;
++	struct pru_rproc *pru;
++
++	rproc = __pru_rproc_get(np, index);
++	if (IS_ERR(rproc))
++		return rproc;
++
++	pru = rproc->priv;
++
++	mutex_lock(&pru->lock);
++
++	if (pru->client_np) {
++		mutex_unlock(&pru->lock);
++		put_device(&rproc->dev);
++		return ERR_PTR(-EBUSY);
++	}
++
++	pru->client_np = np;
++
++	mutex_unlock(&pru->lock);
++
++	if (pru_id)
++		*pru_id = pru->id;
++
++	return rproc;
++}
++EXPORT_SYMBOL_GPL(pru_rproc_get);
++
++/**
++ * pru_rproc_put() - release the PRU rproc resource
++ * @rproc: the rproc resource to release
++ *
++ * Releases the PRU rproc resource and makes it available to other
++ * users.
++ */
++void pru_rproc_put(struct rproc *rproc)
++{
++	struct pru_rproc *pru;
++
++	if (IS_ERR_OR_NULL(rproc) || !is_pru_rproc(rproc->dev.parent))
++		return;
++
++	pru = rproc->priv;
++	if (!pru->client_np)
++		return;
++
++	mutex_lock(&pru->lock);
++	pru->client_np = NULL;
++	mutex_unlock(&pru->lock);
++
++	put_device(&rproc->dev);
++}
++EXPORT_SYMBOL_GPL(pru_rproc_put);
++
+ static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg)
+ {
+ 	return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg);
+@@ -747,14 +863,14 @@ static int pru_rproc_set_id(struct pru_rproc *pru)
+ 	case RTU0_IRAM_ADDR_MASK:
+ 		fallthrough;
+ 	case PRU0_IRAM_ADDR_MASK:
+-		pru->id = 0;
++		pru->id = PRUSS_PRU0;
+ 		break;
+ 	case TX_PRU1_IRAM_ADDR_MASK:
+ 		fallthrough;
+ 	case RTU1_IRAM_ADDR_MASK:
+ 		fallthrough;
+ 	case PRU1_IRAM_ADDR_MASK:
+-		pru->id = 1;
++		pru->id = PRUSS_PRU1;
+ 		break;
+ 	default:
+ 		ret = -EINVAL;
+@@ -816,6 +932,7 @@ static int pru_rproc_probe(struct platform_device *pdev)
+ 	pru->pruss = platform_get_drvdata(ppdev);
+ 	pru->rproc = rproc;
+ 	pru->fw_name = fw_name;
++	mutex_init(&pru->lock);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
+ 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+@@ -897,7 +1014,7 @@ MODULE_DEVICE_TABLE(of, pru_rproc_match);
+ 
+ static struct platform_driver pru_rproc_driver = {
+ 	.driver = {
+-		.name   = "pru-rproc",
++		.name = PRU_RPROC_DRVNAME,
+ 		.of_match_table = pru_rproc_match,
+ 		.suppress_bind_attrs = true,
+ 	},
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+new file mode 100644
+index 000000000000..1a97856b463a
+--- /dev/null
++++ b/include/linux/pruss.h
+@@ -0,0 +1,56 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/**
++ * PRU-ICSS Subsystem user interfaces
++ *
++ * Copyright (C) 2015-2021 Texas Instruments Incorporated - https://www.ti.com
++ *	Suman Anna <s-anna@ti.com>
++ */
++
++#ifndef __LINUX_PRUSS_H
++#define __LINUX_PRUSS_H
++
++#include <linux/device.h>
++#include <linux/types.h>
++
++#define PRU_RPROC_DRVNAME "pru-rproc"
++
++/*
++ * enum pruss_pru_id - PRU core identifiers
++ */
++enum pruss_pru_id {
++	PRUSS_PRU0 = 0,
++	PRUSS_PRU1,
++	PRUSS_NUM_PRUS,
++};
++
++struct device_node;
++
++#if IS_ENABLED(CONFIG_PRU_REMOTEPROC)
++
++struct rproc *pru_rproc_get(struct device_node *np, int index,
++			    enum pruss_pru_id *pru_id);
++void pru_rproc_put(struct rproc *rproc);
++
++#else
++
++static inline struct rproc *
++pru_rproc_get(struct device_node *np, int index, enum pruss_pru_id *pru_id)
++{
++	return ERR_PTR(-EOPNOTSUPP);
++}
++
++static inline void pru_rproc_put(struct rproc *rproc) { }
++
++#endif /* CONFIG_PRU_REMOTEPROC */
++
++static inline bool is_pru_rproc(struct device *dev)
++{
++	const char *drv_name = dev_driver_string(dev);
++
++	if (strncmp(drv_name, PRU_RPROC_DRVNAME, sizeof(PRU_RPROC_DRVNAME)))
++		return false;
++
++	return true;
++}
++
++#endif /* __LINUX_PRUSS_H */

board/PSG/iot2050/files/patches-5.10/0060-remoteproc-pru-Deny-rproc-sysfs-ops-for-PRU-client-d.patch

@@ -0,0 +1,42 @@
+From e611bc6d614a964c3eb9221322da0b69e4ecc699 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Wed, 16 Dec 2020 17:52:37 +0100
+Subject: [PATCH] remoteproc: pru: Deny rproc sysfs ops for PRU client driven
+ boots
+
+The PRU remoteproc driver is not configured for 'auto-boot' by default,
+and allows to be booted either by in-kernel PRU client drivers or by
+userspace using the generic remoteproc sysfs interfaces. The sysfs
+interfaces should not be permitted to change the remoteproc firmwares
+or states when a PRU is being managed by an in-kernel client driver.
+Use the newly introduced remoteproc generic 'deny_sysfs_ops' flag to
+provide these restrictions by setting and clearing it appropriately
+during the PRU acquire and release steps.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 0b57b3f7747f..8fac021adc52 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -226,6 +226,7 @@ struct rproc *pru_rproc_get(struct device_node *np, int index,
+ 	}
+ 
+ 	pru->client_np = np;
++	rproc->deny_sysfs_ops = true;
+ 
+ 	mutex_unlock(&pru->lock);
+ 
+@@ -256,6 +257,7 @@ void pru_rproc_put(struct rproc *rproc)
+ 
+ 	mutex_lock(&pru->lock);
+ 	pru->client_np = NULL;
++	rproc->deny_sysfs_ops = false;
+ 	mutex_unlock(&pru->lock);
+ 
+ 	put_device(&rproc->dev);

board/PSG/iot2050/files/patches-5.10/0061-remoteproc-pru-Add-pru_rproc_set_ctable-function.patch

@@ -0,0 +1,183 @@
+From c7df29e0719acffd6ad4a29572f38559171ee274 Mon Sep 17 00:00:00 2001
+From: Roger Quadros <rogerq@ti.com>
+Date: Fri, 26 Mar 2021 15:43:53 -0500
+Subject: [PATCH] remoteproc: pru: Add pru_rproc_set_ctable() function
+
+Some firmwares expect the OS drivers to configure the CTABLE
+entries publishing dynamically allocated memory regions. For
+example, the PRU Ethernet firmwares use the C28 and C30 entries
+for retrieving the Shared RAM and System SRAM (OCMC) areas
+allocated by the PRU Ethernet client driver.
+
+Provide a way for users to do that through a new API,
+pru_rproc_set_ctable(). The API returns 0 on success and
+a negative value on error.
+
+NOTE:
+The programmable CTABLE entries are typically re-programmed by
+the PRU firmwares when dealing with a certain block of memory
+during block processing. This API provides an interface to the
+PRU client drivers to publish a dynamically allocated memory
+block with the PRU firmware using a CTABLE entry instead of a
+negotiated address in shared memory. Additional synchronization
+may be needed between the PRU client drivers and firmwares if
+different addresses needs to be published at run-time reusing
+the same CTABLE entry.
+
+Co-developed-by: Andrew F. Davis <afd@ti.com>
+Signed-off-by: Andrew F. Davis <afd@ti.com>
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 59 ++++++++++++++++++++++++++++++++++
+ include/linux/pruss.h          | 22 +++++++++++++
+ 2 files changed, 81 insertions(+)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 8fac021adc52..90c097ebc27e 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -118,6 +118,7 @@ struct pru_private_data {
+  * @mapped_irq: virtual interrupt numbers of created fw specific mapping
+  * @pru_interrupt_map: pointer to interrupt mapping description (firmware)
+  * @pru_interrupt_map_sz: pru_interrupt_map size
++ * @rmw_lock: lock for read, modify, write operations on registers
+  * @dbg_single_step: debug state variable to set PRU into single step mode
+  * @dbg_continuous: debug state variable to restore PRU execution mode
+  * @evt_count: number of mapped events
+@@ -135,6 +136,7 @@ struct pru_rproc {
+ 	unsigned int *mapped_irq;
+ 	struct pru_irq_rsc *pru_interrupt_map;
+ 	size_t pru_interrupt_map_sz;
++	spinlock_t rmw_lock; /* register access lock */
+ 	u32 dbg_single_step;
+ 	u32 dbg_continuous;
+ 	u8 evt_count;
+@@ -151,6 +153,23 @@ void pru_control_write_reg(struct pru_rproc *pru, unsigned int reg, u32 val)
+ 	writel_relaxed(val, pru->mem_regions[PRU_IOMEM_CTRL].va + reg);
+ }
+ 
++static inline
++void pru_control_set_reg(struct pru_rproc *pru, unsigned int reg,
++			 u32 mask, u32 set)
++{
++	u32 val;
++	unsigned long flags;
++
++	spin_lock_irqsave(&pru->rmw_lock, flags);
++
++	val = pru_control_read_reg(pru, reg);
++	val &= ~mask;
++	val |= (set & mask);
++	pru_control_write_reg(pru, reg, val);
++
++	spin_unlock_irqrestore(&pru->rmw_lock, flags);
++}
++
+ static struct rproc *__pru_rproc_get(struct device_node *np, int index)
+ {
+ 	struct device_node *rproc_np = NULL;
+@@ -264,6 +283,45 @@ void pru_rproc_put(struct rproc *rproc)
+ }
+ EXPORT_SYMBOL_GPL(pru_rproc_put);
+ 
++/**
++ * pru_rproc_set_ctable() - set the constant table index for the PRU
++ * @rproc: the rproc instance of the PRU
++ * @c: constant table index to set
++ * @addr: physical address to set it to
++ *
++ * Return: 0 on success, or errno in error case.
++ */
++int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr)
++{
++	struct pru_rproc *pru = rproc->priv;
++	unsigned int reg;
++	u32 mask, set;
++	u16 idx;
++	u16 idx_mask;
++
++	if (IS_ERR_OR_NULL(rproc))
++		return -EINVAL;
++
++	if (!rproc->dev.parent || !is_pru_rproc(rproc->dev.parent))
++		return -ENODEV;
++
++	/* pointer is 16 bit and index is 8-bit so mask out the rest */
++	idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF;
++
++	/* ctable uses bit 8 and upwards only */
++	idx = (addr >> 8) & idx_mask;
++
++	/* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */
++	reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1);
++	mask = idx_mask << (16 * (c & 1));
++	set = idx << (16 * (c & 1));
++
++	pru_control_set_reg(pru, reg, mask, set);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(pru_rproc_set_ctable);
++
+ static inline u32 pru_debug_read_reg(struct pru_rproc *pru, unsigned int reg)
+ {
+ 	return readl_relaxed(pru->mem_regions[PRU_IOMEM_DEBUG].va + reg);
+@@ -934,6 +992,7 @@ static int pru_rproc_probe(struct platform_device *pdev)
+ 	pru->pruss = platform_get_drvdata(ppdev);
+ 	pru->rproc = rproc;
+ 	pru->fw_name = fw_name;
++	spin_lock_init(&pru->rmw_lock);
+ 	mutex_init(&pru->lock);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(mem_names); i++) {
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+index 1a97856b463a..e1740ff06962 100644
+--- a/include/linux/pruss.h
++++ b/include/linux/pruss.h
+@@ -23,13 +23,29 @@ enum pruss_pru_id {
+ 	PRUSS_NUM_PRUS,
+ };
+ 
++/*
++ * enum pru_ctable_idx - Configurable Constant table index identifiers
++ */
++enum pru_ctable_idx {
++	PRU_C24 = 0,
++	PRU_C25,
++	PRU_C26,
++	PRU_C27,
++	PRU_C28,
++	PRU_C29,
++	PRU_C30,
++	PRU_C31,
++};
++
+ struct device_node;
++struct rproc;
+ 
+ #if IS_ENABLED(CONFIG_PRU_REMOTEPROC)
+ 
+ struct rproc *pru_rproc_get(struct device_node *np, int index,
+ 			    enum pruss_pru_id *pru_id);
+ void pru_rproc_put(struct rproc *rproc);
++int pru_rproc_set_ctable(struct rproc *rproc, enum pru_ctable_idx c, u32 addr);
+ 
+ #else
+ 
+@@ -41,6 +57,12 @@ pru_rproc_get(struct device_node *np, int index, enum pruss_pru_id *pru_id)
+ 
+ static inline void pru_rproc_put(struct rproc *rproc) { }
+ 
++static inline int pru_rproc_set_ctable(struct rproc *rproc,
++				       enum pru_ctable_idx c, u32 addr)
++{
++	return -EOPNOTSUPP;
++}
++
+ #endif /* CONFIG_PRU_REMOTEPROC */
+ 
+ static inline bool is_pru_rproc(struct device *dev)

board/PSG/iot2050/files/patches-5.10/0062-remoteproc-pru-Configure-firmware-based-on-client-se.patch

@@ -0,0 +1,104 @@
+From 4bf44c69a22f2a8d753dd96c64832b9be0cb1c9f Mon Sep 17 00:00:00 2001
+From: Tero Kristo <t-kristo@ti.com>
+Date: Fri, 26 Mar 2021 15:50:14 -0500
+Subject: [PATCH] remoteproc: pru: Configure firmware based on client setup
+
+Client device node property firmware-name is now used to configure
+firmware for the PRU instances. The default firmware is also
+restored once releasing the PRU resource.
+
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Tero Kristo <t-kristo@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/remoteproc/pru_rproc.c | 39 +++++++++++++++++++++++++++++++++-
+ 1 file changed, 38 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index 90c097ebc27e..c346899d5e3b 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -170,6 +170,23 @@ void pru_control_set_reg(struct pru_rproc *pru, unsigned int reg,
+ 	spin_unlock_irqrestore(&pru->rmw_lock, flags);
+ }
+ 
++/**
++ * pru_rproc_set_firmware() - set firmware for a pru core
++ * @rproc: the rproc instance of the PRU
++ * @fw_name: the new firmware name, or NULL if default is desired
++ *
++ * Return: 0 on success, or errno in error case.
++ */
++static int pru_rproc_set_firmware(struct rproc *rproc, const char *fw_name)
++{
++	struct pru_rproc *pru = rproc->priv;
++
++	if (!fw_name)
++		fw_name = pru->fw_name;
++
++	return rproc_set_firmware(rproc, fw_name);
++}
++
+ static struct rproc *__pru_rproc_get(struct device_node *np, int index)
+ {
+ 	struct device_node *rproc_np = NULL;
+@@ -229,18 +246,22 @@ struct rproc *pru_rproc_get(struct device_node *np, int index,
+ {
+ 	struct rproc *rproc;
+ 	struct pru_rproc *pru;
++	const char *fw_name;
++	struct device *dev;
++	int ret;
+ 
+ 	rproc = __pru_rproc_get(np, index);
+ 	if (IS_ERR(rproc))
+ 		return rproc;
+ 
+ 	pru = rproc->priv;
++	dev = &rproc->dev;
+ 
+ 	mutex_lock(&pru->lock);
+ 
+ 	if (pru->client_np) {
+ 		mutex_unlock(&pru->lock);
+-		put_device(&rproc->dev);
++		put_device(dev);
+ 		return ERR_PTR(-EBUSY);
+ 	}
+ 
+@@ -249,10 +270,24 @@ struct rproc *pru_rproc_get(struct device_node *np, int index,
+ 
+ 	mutex_unlock(&pru->lock);
+ 
++	ret = of_property_read_string_index(np, "firmware-name", index,
++					    &fw_name);
++	if (!ret) {
++		ret = pru_rproc_set_firmware(rproc, fw_name);
++		if (ret) {
++			dev_err(dev, "failed to set firmware: %d\n", ret);
++			goto err;
++		}
++	}
++
+ 	if (pru_id)
+ 		*pru_id = pru->id;
+ 
+ 	return rproc;
++
++err:
++	pru_rproc_put(rproc);
++	return ERR_PTR(ret);
+ }
+ EXPORT_SYMBOL_GPL(pru_rproc_get);
+ 
+@@ -274,6 +309,8 @@ void pru_rproc_put(struct rproc *rproc)
+ 	if (!pru->client_np)
+ 		return;
+ 
++	pru_rproc_set_firmware(rproc, NULL);
++
+ 	mutex_lock(&pru->lock);
+ 	pru->client_np = NULL;
+ 	rproc->deny_sysfs_ops = false;

board/PSG/iot2050/files/patches-5.10/0063-soc-ti-pruss-Add-pruss_get-put-API.patch

@@ -0,0 +1,177 @@
+From 07a129cb887dd76ad8c8b3a104a35c9cbe943205 Mon Sep 17 00:00:00 2001
+From: Tero Kristo <t-kristo@ti.com>
+Date: Fri, 26 Mar 2021 15:58:00 -0500
+Subject: [PATCH] soc: ti: pruss: Add pruss_get()/put() API
+
+Add two new get and put API, pruss_get() and pruss_put() to the
+PRUSS platform driver to allow client drivers to request a handle
+to a PRUSS device. This handle will be used by client drivers to
+request various operations of the PRUSS platform driver through
+additional API that will be added in the following patches.
+
+The pruss_get() function returns the pruss handle corresponding
+to a PRUSS device referenced by a PRU remoteproc instance. The
+pruss_put() is the complimentary function to pruss_get().
+
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Tero Kristo <t-kristo@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/soc/ti/pruss.c       | 60 +++++++++++++++++++++++++++++++++++-
+ include/linux/pruss.h        | 19 ++++++++++++
+ include/linux/pruss_driver.h |  3 +-
+ 3 files changed, 80 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index afc8aae68035..d08adff52094 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -2,10 +2,11 @@
+ /*
+  * PRU-ICSS platform driver for various TI SoCs
+  *
+- * Copyright (C) 2014-2020 Texas Instruments Incorporated - http://www.ti.com/
++ * Copyright (C) 2014-2021 Texas Instruments Incorporated - https://www.ti.com/
+  * Author(s):
+  *	Suman Anna <s-anna@ti.com>
+  *	Andrew F. Davis <afd@ti.com>
++ *	Tero Kristo <t-kristo@ti.com>
+  */
+ 
+ #include <linux/clk-provider.h>
+@@ -18,6 +19,7 @@
+ #include <linux/pm_runtime.h>
+ #include <linux/pruss_driver.h>
+ #include <linux/regmap.h>
++#include <linux/remoteproc.h>
+ #include <linux/slab.h>
+ 
+ /**
+@@ -30,6 +32,62 @@ struct pruss_private_data {
+ 	bool has_core_mux_clock;
+ };
+ 
++/**
++ * pruss_get() - get the pruss for a given PRU remoteproc
++ * @rproc: remoteproc handle of a PRU instance
++ *
++ * Finds the parent pruss device for a PRU given the @rproc handle of the
++ * PRU remote processor. This function increments the pruss device's refcount,
++ * so always use pruss_put() to decrement it back once pruss isn't needed
++ * anymore.
++ *
++ * Return: pruss handle on success, and an ERR_PTR on failure using one
++ * of the following error values
++ *    -EINVAL if invalid parameter
++ *    -ENODEV if PRU device or PRUSS device is not found
++ */
++struct pruss *pruss_get(struct rproc *rproc)
++{
++	struct pruss *pruss;
++	struct device *dev;
++	struct platform_device *ppdev;
++
++	if (IS_ERR_OR_NULL(rproc))
++		return ERR_PTR(-EINVAL);
++
++	dev = &rproc->dev;
++
++	/* make sure it is PRU rproc */
++	if (!dev->parent || !is_pru_rproc(dev->parent))
++		return ERR_PTR(-ENODEV);
++
++	ppdev = to_platform_device(dev->parent->parent);
++	pruss = platform_get_drvdata(ppdev);
++	if (!pruss)
++		return ERR_PTR(-ENODEV);
++
++	get_device(pruss->dev);
++
++	return pruss;
++}
++EXPORT_SYMBOL_GPL(pruss_get);
++
++/**
++ * pruss_put() - decrement pruss device's usecount
++ * @pruss: pruss handle
++ *
++ * Complimentary function for pruss_get(). Needs to be called
++ * after the PRUSS is used, and only if the pruss_get() succeeds.
++ */
++void pruss_put(struct pruss *pruss)
++{
++	if (IS_ERR_OR_NULL(pruss))
++		return;
++
++	put_device(pruss->dev);
++}
++EXPORT_SYMBOL_GPL(pruss_put);
++
+ static void pruss_of_free_clk_provider(void *data)
+ {
+ 	struct device_node *clk_mux_np = data;
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+index e1740ff06962..2e1f519255b9 100644
+--- a/include/linux/pruss.h
++++ b/include/linux/pruss.h
+@@ -4,12 +4,14 @@
+  *
+  * Copyright (C) 2015-2021 Texas Instruments Incorporated - https://www.ti.com
+  *	Suman Anna <s-anna@ti.com>
++ *	Tero Kristo <t-kristo@ti.com>
+  */
+ 
+ #ifndef __LINUX_PRUSS_H
+ #define __LINUX_PRUSS_H
+ 
+ #include <linux/device.h>
++#include <linux/err.h>
+ #include <linux/types.h>
+ 
+ #define PRU_RPROC_DRVNAME "pru-rproc"
+@@ -39,6 +41,23 @@ enum pru_ctable_idx {
+ 
+ struct device_node;
+ struct rproc;
++struct pruss;
++
++#if IS_ENABLED(CONFIG_TI_PRUSS)
++
++struct pruss *pruss_get(struct rproc *rproc);
++void pruss_put(struct pruss *pruss);
++
++#else
++
++static inline struct pruss *pruss_get(struct rproc *rproc)
++{
++	return ERR_PTR(-EOPNOTSUPP);
++}
++
++static inline void pruss_put(struct pruss *pruss) { }
++
++#endif /* CONFIG_TI_PRUSS */
+ 
+ #if IS_ENABLED(CONFIG_PRU_REMOTEPROC)
+ 
+diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h
+index ecfded30ed05..4d1321f0d326 100644
+--- a/include/linux/pruss_driver.h
++++ b/include/linux/pruss_driver.h
+@@ -2,13 +2,14 @@
+ /*
+  * PRU-ICSS sub-system specific definitions
+  *
+- * Copyright (C) 2014-2020 Texas Instruments Incorporated - http://www.ti.com/
++ * Copyright (C) 2014-2021 Texas Instruments Incorporated - https://www.ti.com/
+  *	Suman Anna <s-anna@ti.com>
+  */
+ 
+ #ifndef _PRUSS_DRIVER_H_
+ #define _PRUSS_DRIVER_H_
+ 
++#include <linux/pruss.h>
+ #include <linux/types.h>
+ 
+ /*

board/PSG/iot2050/files/patches-5.10/0064-soc-ti-pruss-Add-pruss_-request-release-_mem_region-.patch

@@ -0,0 +1,236 @@
+From 5656404835fbe4b6f5d756826e9d0d5f011ede11 Mon Sep 17 00:00:00 2001
+From: "Andrew F. Davis" <afd@ti.com>
+Date: Fri, 26 Mar 2021 16:11:42 -0500
+Subject: [PATCH] soc: ti: pruss: Add pruss_{request,release}_mem_region() API
+
+Add two new API - pruss_request_mem_region() & pruss_release_mem_region(),
+to the PRUSS platform driver to allow client drivers to acquire and release
+the common memory resources present within a PRU-ICSS subsystem. This
+allows the client drivers to directly manipulate the respective memories,
+as per their design contract with the associated firmware.
+
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Andrew F. Davis <afd@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/soc/ti/pruss.c       | 78 ++++++++++++++++++++++++++++++++++++
+ include/linux/pruss.h        | 39 ++++++++++++++++++
+ include/linux/pruss_driver.h | 27 +++----------
+ 3 files changed, 122 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index d08adff52094..dc1470fa33d0 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -88,6 +88,83 @@ void pruss_put(struct pruss *pruss)
+ }
+ EXPORT_SYMBOL_GPL(pruss_put);
+ 
++/**
++ * pruss_request_mem_region() - request a memory resource
++ * @pruss: the pruss instance
++ * @mem_id: the memory resource id
++ * @region: pointer to memory region structure to be filled in
++ *
++ * This function allows a client driver to request a memory resource,
++ * and if successful, will let the client driver own the particular
++ * memory region until released using the pruss_release_mem_region()
++ * API.
++ *
++ * Return: 0 if requested memory region is available with the memory region
++ * values returned in memory pointed by @region, an error otherwise
++ */
++int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id,
++			     struct pruss_mem_region *region)
++{
++	if (!pruss || !region || mem_id >= PRUSS_MEM_MAX)
++		return -EINVAL;
++
++	mutex_lock(&pruss->lock);
++
++	if (pruss->mem_in_use[mem_id]) {
++		mutex_unlock(&pruss->lock);
++		return -EBUSY;
++	}
++
++	*region = pruss->mem_regions[mem_id];
++	pruss->mem_in_use[mem_id] = region;
++
++	mutex_unlock(&pruss->lock);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(pruss_request_mem_region);
++
++/**
++ * pruss_release_mem_region() - release a memory resource
++ * @pruss: the pruss instance
++ * @region: the memory region to release
++ *
++ * This function is the complimentary function to
++ * pruss_request_mem_region(), and allows the client drivers to
++ * release back a memory resource.
++ *
++ * Return: 0 on success, an error code otherwise
++ */
++int pruss_release_mem_region(struct pruss *pruss,
++			     struct pruss_mem_region *region)
++{
++	int id;
++
++	if (!pruss || !region)
++		return -EINVAL;
++
++	mutex_lock(&pruss->lock);
++
++	/* find out the memory region being released */
++	for (id = 0; id < PRUSS_MEM_MAX; id++) {
++		if (pruss->mem_in_use[id] == region)
++			break;
++	}
++
++	if (id == PRUSS_MEM_MAX) {
++		mutex_unlock(&pruss->lock);
++		return -EINVAL;
++	}
++
++	pruss->mem_in_use[id] = NULL;
++	memset(region, 0, sizeof(*region));
++
++	mutex_unlock(&pruss->lock);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(pruss_release_mem_region);
++
+ static void pruss_of_free_clk_provider(void *data)
+ {
+ 	struct device_node *clk_mux_np = data;
+@@ -290,6 +367,7 @@ static int pruss_probe(struct platform_device *pdev)
+ 		return -ENOMEM;
+ 
+ 	pruss->dev = dev;
++	mutex_init(&pruss->lock);
+ 
+ 	child = of_get_child_by_name(np, "memories");
+ 	if (!child) {
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+index 2e1f519255b9..40de553d4446 100644
+--- a/include/linux/pruss.h
++++ b/include/linux/pruss.h
+@@ -39,6 +39,28 @@ enum pru_ctable_idx {
+ 	PRU_C31,
+ };
+ 
++/*
++ * enum pruss_mem - PRUSS memory range identifiers
++ */
++enum pruss_mem {
++	PRUSS_MEM_DRAM0 = 0,
++	PRUSS_MEM_DRAM1,
++	PRUSS_MEM_SHRD_RAM2,
++	PRUSS_MEM_MAX,
++};
++
++/**
++ * struct pruss_mem_region - PRUSS memory region structure
++ * @va: kernel virtual address of the PRUSS memory region
++ * @pa: physical (bus) address of the PRUSS memory region
++ * @size: size of the PRUSS memory region
++ */
++struct pruss_mem_region {
++	void __iomem *va;
++	phys_addr_t pa;
++	size_t size;
++};
++
+ struct device_node;
+ struct rproc;
+ struct pruss;
+@@ -47,6 +69,10 @@ struct pruss;
+ 
+ struct pruss *pruss_get(struct rproc *rproc);
+ void pruss_put(struct pruss *pruss);
++int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id,
++			     struct pruss_mem_region *region);
++int pruss_release_mem_region(struct pruss *pruss,
++			     struct pruss_mem_region *region);
+ 
+ #else
+ 
+@@ -57,6 +83,19 @@ static inline struct pruss *pruss_get(struct rproc *rproc)
+ 
+ static inline void pruss_put(struct pruss *pruss) { }
+ 
++static inline int pruss_request_mem_region(struct pruss *pruss,
++					   enum pruss_mem mem_id,
++					   struct pruss_mem_region *region)
++{
++	return -EOPNOTSUPP;
++}
++
++static inline int pruss_release_mem_region(struct pruss *pruss,
++					   struct pruss_mem_region *region)
++{
++	return -EOPNOTSUPP;
++}
++
+ #endif /* CONFIG_TI_PRUSS */
+ 
+ #if IS_ENABLED(CONFIG_PRU_REMOTEPROC)
+diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h
+index 4d1321f0d326..f1d1197fd91a 100644
+--- a/include/linux/pruss_driver.h
++++ b/include/linux/pruss_driver.h
+@@ -9,37 +9,18 @@
+ #ifndef _PRUSS_DRIVER_H_
+ #define _PRUSS_DRIVER_H_
+ 
++#include <linux/mutex.h>
+ #include <linux/pruss.h>
+ #include <linux/types.h>
+ 
+-/*
+- * enum pruss_mem - PRUSS memory range identifiers
+- */
+-enum pruss_mem {
+-	PRUSS_MEM_DRAM0 = 0,
+-	PRUSS_MEM_DRAM1,
+-	PRUSS_MEM_SHRD_RAM2,
+-	PRUSS_MEM_MAX,
+-};
+-
+-/**
+- * struct pruss_mem_region - PRUSS memory region structure
+- * @va: kernel virtual address of the PRUSS memory region
+- * @pa: physical (bus) address of the PRUSS memory region
+- * @size: size of the PRUSS memory region
+- */
+-struct pruss_mem_region {
+-	void __iomem *va;
+-	phys_addr_t pa;
+-	size_t size;
+-};
+-
+ /**
+  * struct pruss - PRUSS parent structure
+  * @dev: pruss device pointer
+  * @cfg_base: base iomap for CFG region
+  * @cfg_regmap: regmap for config region
+  * @mem_regions: data for each of the PRUSS memory regions
++ * @mem_in_use: to indicate if memory resource is in use
++ * @lock: mutex to serialize access to resources
+  * @core_clk_mux: clk handle for PRUSS CORE_CLK_MUX
+  * @iep_clk_mux: clk handle for PRUSS IEP_CLK_MUX
+  */
+@@ -48,6 +29,8 @@ struct pruss {
+ 	void __iomem *cfg_base;
+ 	struct regmap *cfg_regmap;
+ 	struct pruss_mem_region mem_regions[PRUSS_MEM_MAX];
++	struct pruss_mem_region *mem_in_use[PRUSS_MEM_MAX];
++	struct mutex lock; /* PRU resource lock */
+ 	struct clk *core_clk_mux;
+ 	struct clk *iep_clk_mux;
+ };

board/PSG/iot2050/files/patches-5.10/0065-soc-ti-pruss-Add-pruss_cfg_read-update-API.patch

@@ -0,0 +1,210 @@
+From 08fbca565e8bfebb618b1a0be66759f8bae3cef2 Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 26 Mar 2021 16:27:34 -0500
+Subject: [PATCH] soc: ti: pruss: Add pruss_cfg_read()/update() API
+
+Add two new generic API pruss_cfg_read() and pruss_cfg_update() to
+the PRUSS platform driver to allow other drivers to read and program
+respectively a register within the PRUSS CFG sub-module represented
+by a syscon driver. This interface provides a simple way for client
+drivers without having them to include and parse the CFG syscon node
+within their respective device nodes. Various useful registers and
+macros for certain register bit-fields and their values have also
+been added.
+
+It is the responsibility of the client drivers to reconfigure or
+reset a particular register upon any failures.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/soc/ti/pruss.c |  41 +++++++++++++++++
+ include/linux/pruss.h  | 102 +++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 143 insertions(+)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index dc1470fa33d0..8841d85a0a0d 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -165,6 +165,47 @@ int pruss_release_mem_region(struct pruss *pruss,
+ }
+ EXPORT_SYMBOL_GPL(pruss_release_mem_region);
+ 
++/**
++ * pruss_cfg_read() - read a PRUSS CFG sub-module register
++ * @pruss: the pruss instance handle
++ * @reg: register offset within the CFG sub-module
++ * @val: pointer to return the value in
++ *
++ * Reads a given register within the PRUSS CFG sub-module and
++ * returns it through the passed-in @val pointer
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val)
++{
++	if (IS_ERR_OR_NULL(pruss))
++		return -EINVAL;
++
++	return regmap_read(pruss->cfg_regmap, reg, val);
++}
++EXPORT_SYMBOL_GPL(pruss_cfg_read);
++
++/**
++ * pruss_cfg_update() - configure a PRUSS CFG sub-module register
++ * @pruss: the pruss instance handle
++ * @reg: register offset within the CFG sub-module
++ * @mask: bit mask to use for programming the @val
++ * @val: value to write
++ *
++ * Programs a given register within the PRUSS CFG sub-module
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++int pruss_cfg_update(struct pruss *pruss, unsigned int reg,
++		     unsigned int mask, unsigned int val)
++{
++	if (IS_ERR_OR_NULL(pruss))
++		return -EINVAL;
++
++	return regmap_update_bits(pruss->cfg_regmap, reg, mask, val);
++}
++EXPORT_SYMBOL_GPL(pruss_cfg_update);
++
+ static void pruss_of_free_clk_provider(void *data)
+ {
+ 	struct device_node *clk_mux_np = data;
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+index 40de553d4446..a4f59a46c331 100644
+--- a/include/linux/pruss.h
++++ b/include/linux/pruss.h
+@@ -10,12 +10,99 @@
+ #ifndef __LINUX_PRUSS_H
+ #define __LINUX_PRUSS_H
+ 
++#include <linux/bits.h>
+ #include <linux/device.h>
+ #include <linux/err.h>
+ #include <linux/types.h>
+ 
+ #define PRU_RPROC_DRVNAME "pru-rproc"
+ 
++/*
++ * PRU_ICSS_CFG registers
++ * SYSCFG, ISRP, ISP, IESP, IECP, SCRP applicable on AMxxxx devices only
++ */
++#define PRUSS_CFG_REVID		0x00
++#define PRUSS_CFG_SYSCFG	0x04
++#define PRUSS_CFG_GPCFG(x)	(0x08 + (x) * 4)
++#define PRUSS_CFG_CGR		0x10
++#define PRUSS_CFG_ISRP		0x14
++#define PRUSS_CFG_ISP		0x18
++#define PRUSS_CFG_IESP		0x1C
++#define PRUSS_CFG_IECP		0x20
++#define PRUSS_CFG_SCRP		0x24
++#define PRUSS_CFG_PMAO		0x28
++#define PRUSS_CFG_MII_RT	0x2C
++#define PRUSS_CFG_IEPCLK	0x30
++#define PRUSS_CFG_SPP		0x34
++#define PRUSS_CFG_PIN_MX	0x40
++
++/* PRUSS_GPCFG register bits */
++#define PRUSS_GPCFG_PRU_GPO_SH_SEL		BIT(25)
++
++#define PRUSS_GPCFG_PRU_DIV1_SHIFT		20
++#define PRUSS_GPCFG_PRU_DIV1_MASK		GENMASK(24, 20)
++
++#define PRUSS_GPCFG_PRU_DIV0_SHIFT		15
++#define PRUSS_GPCFG_PRU_DIV0_MASK		GENMASK(15, 19)
++
++#define PRUSS_GPCFG_PRU_GPO_MODE		BIT(14)
++#define PRUSS_GPCFG_PRU_GPO_MODE_DIRECT		0
++#define PRUSS_GPCFG_PRU_GPO_MODE_SERIAL		BIT(14)
++
++#define PRUSS_GPCFG_PRU_GPI_SB			BIT(13)
++
++#define PRUSS_GPCFG_PRU_GPI_DIV1_SHIFT		8
++#define PRUSS_GPCFG_PRU_GPI_DIV1_MASK		GENMASK(12, 8)
++
++#define PRUSS_GPCFG_PRU_GPI_DIV0_SHIFT		3
++#define PRUSS_GPCFG_PRU_GPI_DIV0_MASK		GENMASK(7, 3)
++
++#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_POSITIVE	0
++#define PRUSS_GPCFG_PRU_GPI_CLK_MODE_NEGATIVE	BIT(2)
++#define PRUSS_GPCFG_PRU_GPI_CLK_MODE		BIT(2)
++
++#define PRUSS_GPCFG_PRU_GPI_MODE_MASK		GENMASK(1, 0)
++#define PRUSS_GPCFG_PRU_GPI_MODE_SHIFT		0
++
++#define PRUSS_GPCFG_PRU_MUX_SEL_SHIFT		26
++#define PRUSS_GPCFG_PRU_MUX_SEL_MASK		GENMASK(29, 26)
++
++/* PRUSS_MII_RT register bits */
++#define PRUSS_MII_RT_EVENT_EN			BIT(0)
++
++/* PRUSS_SPP register bits */
++#define PRUSS_SPP_XFER_SHIFT_EN			BIT(1)
++#define PRUSS_SPP_PRU1_PAD_HP_EN		BIT(0)
++
++/*
++ * enum pruss_gp_mux_sel - PRUSS GPI/O Mux modes for the
++ * PRUSS_GPCFG0/1 registers
++ *
++ * NOTE: The below defines are the most common values, but there
++ * are some exceptions like on 66AK2G, where the RESERVED and MII2
++ * values are interchanged. Also, this bit-field does not exist on
++ * AM335x SoCs
++ */
++enum pruss_gp_mux_sel {
++	PRUSS_GP_MUX_SEL_GP = 0,
++	PRUSS_GP_MUX_SEL_ENDAT,
++	PRUSS_GP_MUX_SEL_RESERVED,
++	PRUSS_GP_MUX_SEL_SD,
++	PRUSS_GP_MUX_SEL_MII2,
++	PRUSS_GP_MUX_SEL_MAX,
++};
++
++/*
++ * enum pruss_gpi_mode - PRUSS GPI configuration modes, used
++ *			 to program the PRUSS_GPCFG0/1 registers
++ */
++enum pruss_gpi_mode {
++	PRUSS_GPI_MODE_DIRECT = 0,
++	PRUSS_GPI_MODE_PARALLEL,
++	PRUSS_GPI_MODE_28BIT_SHIFT,
++	PRUSS_GPI_MODE_MII,
++};
++
+ /*
+  * enum pruss_pru_id - PRU core identifiers
+  */
+@@ -73,6 +160,9 @@ int pruss_request_mem_region(struct pruss *pruss, enum pruss_mem mem_id,
+ 			     struct pruss_mem_region *region);
+ int pruss_release_mem_region(struct pruss *pruss,
+ 			     struct pruss_mem_region *region);
++int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val);
++int pruss_cfg_update(struct pruss *pruss, unsigned int reg,
++		     unsigned int mask, unsigned int val);
+ 
+ #else
+ 
+@@ -96,6 +186,18 @@ static inline int pruss_release_mem_region(struct pruss *pruss,
+ 	return -EOPNOTSUPP;
+ }
+ 
++static inline int pruss_cfg_read(struct pruss *pruss, unsigned int reg,
++				 unsigned int *val)
++{
++	return -EOPNOTSUPP;
++}
++
++static inline int pruss_cfg_update(struct pruss *pruss, unsigned int reg,
++				   unsigned int mask, unsigned int val)
++{
++	return -EOPNOTSUPP;
++}
++
+ #endif /* CONFIG_TI_PRUSS */
+ 
+ #if IS_ENABLED(CONFIG_PRU_REMOTEPROC)

board/PSG/iot2050/files/patches-5.10/0066-soc-ti-pruss-Add-helper-functions-to-set-GPI-mode-MI.patch

@@ -0,0 +1,83 @@
+From cef98ec97a1bbdb6982778cc935a1aa66ea0528f Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 11 Dec 2020 19:48:09 +0100
+Subject: [PATCH] soc: ti: pruss: Add helper functions to set GPI mode,
+ MII_RT_event and XFR
+
+The PRUSS CFG module is represented as a syscon node and is currently
+managed by the PRUSS platform driver. Add easy accessor functions to set
+GPI mode, MII_RT event enable/disable and XFR (XIN XOUT) enable/disable
+to enable the PRUSS Ethernet usecase. These functions reuse the generic
+pruss_cfg_update() API function.
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ include/linux/pruss.h | 55 +++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+index a4f59a46c331..ba5b728d5015 100644
+--- a/include/linux/pruss.h
++++ b/include/linux/pruss.h
+@@ -235,4 +235,59 @@ static inline bool is_pru_rproc(struct device *dev)
+ 	return true;
+ }
+ 
++/**
++ * pruss_cfg_gpimode() - set the GPI mode of the PRU
++ * @pruss: the pruss instance handle
++ * @pru_id: id of the PRU core within the PRUSS
++ * @mode: GPI mode to set
++ *
++ * Sets the GPI mode for a given PRU by programming the
++ * corresponding PRUSS_CFG_GPCFGx register
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++static inline int pruss_cfg_gpimode(struct pruss *pruss,
++				    enum pruss_pru_id pru_id,
++				    enum pruss_gpi_mode mode)
++{
++	if (pru_id < 0 || pru_id >= PRUSS_NUM_PRUS)
++		return -EINVAL;
++
++	return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id),
++				PRUSS_GPCFG_PRU_GPI_MODE_MASK,
++				mode << PRUSS_GPCFG_PRU_GPI_MODE_SHIFT);
++}
++
++/**
++ * pruss_cfg_miirt_enable() - Enable/disable MII RT Events
++ * @pruss: the pruss instance
++ * @enable: enable/disable
++ *
++ * Enable/disable the MII RT Events for the PRUSS.
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++static inline int pruss_cfg_miirt_enable(struct pruss *pruss, bool enable)
++{
++	u32 set = enable ? PRUSS_MII_RT_EVENT_EN : 0;
++
++	return pruss_cfg_update(pruss, PRUSS_CFG_MII_RT,
++				PRUSS_MII_RT_EVENT_EN, set);
++}
++
++/**
++ * pruss_cfg_xfr_enable() - Enable/disable XIN XOUT shift functionality
++ * @pruss: the pruss instance
++ * @enable: enable/disable
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++static inline int pruss_cfg_xfr_enable(struct pruss *pruss, bool enable)
++{
++	u32 set = enable ? PRUSS_SPP_XFER_SHIFT_EN : 0;
++
++	return pruss_cfg_update(pruss, PRUSS_CFG_SPP,
++				PRUSS_SPP_XFER_SHIFT_EN, set);
++}
++
+ #endif /* __LINUX_PRUSS_H */

board/PSG/iot2050/files/patches-5.10/0067-soc-ti-pruss-Add-helper-function-to-enable-OCP-maste.patch

@@ -0,0 +1,179 @@
+From dcd56dcacc780840539cea865b89fcedcb63d56e Mon Sep 17 00:00:00 2001
+From: Suman Anna <s-anna@ti.com>
+Date: Fri, 26 Mar 2021 16:38:11 -0500
+Subject: [PATCH] soc: ti: pruss: Add helper function to enable OCP master
+ ports
+
+The PRU-ICSS subsystem on OMAP-architecture based SoCS (AM33xx, AM437x
+and AM57xx SoCs) has a control bit STANDBY_INIT in the PRUSS_CFG register
+to initiate a Standby sequence (when set) and trigger a MStandby request
+to the SoC's PRCM module. This same bit is also used to enable the OCP
+master ports (when cleared). The clearing of the STANDBY_INIT bit requires
+an acknowledgment from PRCM and is done through the monitoring of the
+PRUSS_SYSCFG.SUB_MWAIT bit.
+
+Add a helper function pruss_cfg_ocp_master_ports() to allow the PRU
+client drivers to control this bit and enable or disable the firmware
+running on PRU cores access to any peripherals or memory to achieve
+desired functionality. The access is disabled by default on power-up
+and on any suspend (context is not maintained).
+
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ drivers/soc/ti/pruss.c | 81 ++++++++++++++++++++++++++++++++++++++++--
+ include/linux/pruss.h  |  6 ++++
+ 2 files changed, 85 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c
+index 8841d85a0a0d..1254495b7c45 100644
+--- a/drivers/soc/ti/pruss.c
++++ b/drivers/soc/ti/pruss.c
+@@ -22,14 +22,19 @@
+ #include <linux/remoteproc.h>
+ #include <linux/slab.h>
+ 
++#define SYSCFG_STANDBY_INIT	BIT(4)
++#define SYSCFG_SUB_MWAIT_READY	BIT(5)
++
+ /**
+  * struct pruss_private_data - PRUSS driver private data
+  * @has_no_sharedram: flag to indicate the absence of PRUSS Shared Data RAM
+  * @has_core_mux_clock: flag to indicate the presence of PRUSS core clock
++ * @has_ocp_syscfg: flag to indicate if OCP SYSCFG is present
+  */
+ struct pruss_private_data {
+ 	bool has_no_sharedram;
+ 	bool has_core_mux_clock;
++	bool has_ocp_syscfg;
+ };
+ 
+ /**
+@@ -206,6 +211,72 @@ int pruss_cfg_update(struct pruss *pruss, unsigned int reg,
+ }
+ EXPORT_SYMBOL_GPL(pruss_cfg_update);
+ 
++/**
++ * pruss_cfg_ocp_master_ports() - configure PRUSS OCP master ports
++ * @pruss: the pruss instance handle
++ * @enable: set to true for enabling or false for disabling the OCP master ports
++ *
++ * This function programs the PRUSS_SYSCFG.STANDBY_INIT bit either to enable or
++ * disable the OCP master ports (applicable only on SoCs using OCP interconnect
++ * like the OMAP family). Clearing the bit achieves dual functionalities - one
++ * is to deassert the MStandby signal to the device PRCM, and the other is to
++ * enable OCP master ports to allow accesses outside of the PRU-ICSS. The
++ * function has to wait for the PRCM to acknowledge through the monitoring of
++ * the PRUSS_SYSCFG.SUB_MWAIT bit when enabling master ports. Setting the bit
++ * disables the master access, and also signals the PRCM that the PRUSS is ready
++ * for Standby.
++ *
++ * Return: 0 on success, or an error code otherwise. ETIMEDOUT is returned
++ * when the ready-state fails.
++ */
++int pruss_cfg_ocp_master_ports(struct pruss *pruss, bool enable)
++{
++	int ret;
++	u32 syscfg_val, i;
++	const struct pruss_private_data *data;
++
++	if (IS_ERR_OR_NULL(pruss))
++		return -EINVAL;
++
++	data = of_device_get_match_data(pruss->dev);
++
++	/* nothing to do on non OMAP-SoCs */
++	if (!data || !data->has_ocp_syscfg)
++		return 0;
++
++	/* assert the MStandby signal during disable path */
++	if (!enable)
++		return pruss_cfg_update(pruss, PRUSS_CFG_SYSCFG,
++					SYSCFG_STANDBY_INIT,
++					SYSCFG_STANDBY_INIT);
++
++	/* enable the OCP master ports and disable MStandby */
++	ret = pruss_cfg_update(pruss, PRUSS_CFG_SYSCFG, SYSCFG_STANDBY_INIT, 0);
++	if (ret)
++		return ret;
++
++	/* wait till we are ready for transactions - delay is arbitrary */
++	for (i = 0; i < 10; i++) {
++		ret = pruss_cfg_read(pruss, PRUSS_CFG_SYSCFG, &syscfg_val);
++		if (ret)
++			goto disable;
++
++		if (!(syscfg_val & SYSCFG_SUB_MWAIT_READY))
++			return 0;
++
++		udelay(5);
++	}
++
++	dev_err(pruss->dev, "timeout waiting for SUB_MWAIT_READY\n");
++	ret = -ETIMEDOUT;
++
++disable:
++	pruss_cfg_update(pruss, PRUSS_CFG_SYSCFG, SYSCFG_STANDBY_INIT,
++			 SYSCFG_STANDBY_INIT);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(pruss_cfg_ocp_master_ports);
++
+ static void pruss_of_free_clk_provider(void *data)
+ {
+ 	struct device_node *clk_mux_np = data;
+@@ -497,10 +568,16 @@ static int pruss_remove(struct platform_device *pdev)
+ /* instance-specific driver private data */
+ static const struct pruss_private_data am437x_pruss1_data = {
+ 	.has_no_sharedram = false,
++	.has_ocp_syscfg = true,
+ };
+ 
+ static const struct pruss_private_data am437x_pruss0_data = {
+ 	.has_no_sharedram = true,
++	.has_ocp_syscfg = false,
++};
++
++static const struct pruss_private_data am33xx_am57xx_data = {
++	.has_ocp_syscfg = true,
+ };
+ 
+ static const struct pruss_private_data am65x_j721e_pruss_data = {
+@@ -508,10 +585,10 @@ static const struct pruss_private_data am65x_j721e_pruss_data = {
+ };
+ 
+ static const struct of_device_id pruss_of_match[] = {
+-	{ .compatible = "ti,am3356-pruss" },
++	{ .compatible = "ti,am3356-pruss", .data = &am33xx_am57xx_data },
+ 	{ .compatible = "ti,am4376-pruss0", .data = &am437x_pruss0_data, },
+ 	{ .compatible = "ti,am4376-pruss1", .data = &am437x_pruss1_data, },
+-	{ .compatible = "ti,am5728-pruss" },
++	{ .compatible = "ti,am5728-pruss", .data = &am33xx_am57xx_data },
+ 	{ .compatible = "ti,k2g-pruss" },
+ 	{ .compatible = "ti,am654-icssg", .data = &am65x_j721e_pruss_data, },
+ 	{ .compatible = "ti,j721e-icssg", .data = &am65x_j721e_pruss_data, },
+diff --git a/include/linux/pruss.h b/include/linux/pruss.h
+index ba5b728d5015..5fdd6f03446d 100644
+--- a/include/linux/pruss.h
++++ b/include/linux/pruss.h
+@@ -163,6 +163,7 @@ int pruss_release_mem_region(struct pruss *pruss,
+ int pruss_cfg_read(struct pruss *pruss, unsigned int reg, unsigned int *val);
+ int pruss_cfg_update(struct pruss *pruss, unsigned int reg,
+ 		     unsigned int mask, unsigned int val);
++int pruss_cfg_ocp_master_ports(struct pruss *pruss, bool enable);
+ 
+ #else
+ 
+@@ -198,6 +199,11 @@ static inline int pruss_cfg_update(struct pruss *pruss, unsigned int reg,
+ 	return -EOPNOTSUPP;
+ }
+ 
++static inline int pruss_cfg_ocp_master_ports(struct pruss *pruss, bool enable)
++{
++	return -EOPNOTSUPP;
++}
++
+ #endif /* CONFIG_TI_PRUSS */
+ 
+ #if IS_ENABLED(CONFIG_PRU_REMOTEPROC)

board/PSG/iot2050/files/patches-5.10/0068-soc-ti-pruss-Add-helper-functions-to-get-set-PRUSS_C.patch

@@ -0,0 +1,72 @@
+From 0645d69bced1b73566fedecdfb09bdcb86997c5e Mon Sep 17 00:00:00 2001
+From: Tero Kristo <t-kristo@ti.com>
+Date: Sat, 27 Mar 2021 09:24:51 -0500
+Subject: [PATCH] soc: ti: pruss: Add helper functions to get/set
+ PRUSS_CFG_GPMUX
+
+Add two new helper functions pruss_cfg_get_gpmux() & pruss_cfg_set_gpmux()
+to get and set the GP MUX mode for programming the PRUSS internal wrapper
+mux functionality as needed by usecases.
+
+Co-developed-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Suman Anna <s-anna@ti.com>
+Signed-off-by: Tero Kristo <t-kristo@ti.com>
+Co-developed-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+Signed-off-by: Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>
+---
+ include/linux/pruss_driver.h | 44 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+diff --git a/include/linux/pruss_driver.h b/include/linux/pruss_driver.h
+index f1d1197fd91a..d6abfdd17631 100644
+--- a/include/linux/pruss_driver.h
++++ b/include/linux/pruss_driver.h
+@@ -35,4 +35,48 @@ struct pruss {
+ 	struct clk *iep_clk_mux;
+ };
+ 
++/**
++ * pruss_cfg_get_gpmux() - get the current GPMUX value for a PRU device
++ * @pruss: pruss instance
++ * @pru_id: PRU identifier (0-1)
++ * @mux: pointer to store the current mux value into
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++static inline int pruss_cfg_get_gpmux(struct pruss *pruss,
++				      enum pruss_pru_id pru_id, u8 *mux)
++{
++	int ret = 0;
++	u32 val;
++
++	if (pru_id < 0 || pru_id >= PRUSS_NUM_PRUS)
++		return -EINVAL;
++
++	ret = pruss_cfg_read(pruss, PRUSS_CFG_GPCFG(pru_id), &val);
++	if (!ret)
++		*mux = (u8)((val & PRUSS_GPCFG_PRU_MUX_SEL_MASK) >>
++			    PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
++	return ret;
++}
++
++/**
++ * pruss_cfg_set_gpmux() - set the GPMUX value for a PRU device
++ * @pruss: pruss instance
++ * @pru_id: PRU identifier (0-1)
++ * @mux: new mux value for PRU
++ *
++ * Return: 0 on success, or an error code otherwise
++ */
++static inline int pruss_cfg_set_gpmux(struct pruss *pruss,
++				      enum pruss_pru_id pru_id, u8 mux)
++{
++	if (mux >= PRUSS_GP_MUX_SEL_MAX ||
++	    pru_id < 0 || pru_id >= PRUSS_NUM_PRUS)
++		return -EINVAL;
++
++	return pruss_cfg_update(pruss, PRUSS_CFG_GPCFG(pru_id),
++				PRUSS_GPCFG_PRU_MUX_SEL_MASK,
++				(u32)mux << PRUSS_GPCFG_PRU_MUX_SEL_SHIFT);
++}
++
+ #endif	/* _PRUSS_DRIVER_H_ */

board/PSG/iot2050/files/patches-5.10/0069-remoteproc-pru-add-support-for-configuring-GPMUX-bas.patch

@@ -0,0 +1,76 @@
+From deb00f00f17206b2083f80f3f722963c1c3a80a9 Mon Sep 17 00:00:00 2001
+From: Tero Kristo <t-kristo@ti.com>
+Date: Sat, 27 Mar 2021 10:11:42 -0500
+Subject: [PATCH] remoteproc/pru: add support for configuring GPMUX based on
+ client setup
+
+Client device node property ti,pruss-gp-mux-sel can now be used to
+configure the GPMUX config value for PRU.
+
+Signed-off-by: Tero Kristo <t-kristo@ti.com>
+[s-anna@ti.com: simplify the pru id usage]
+Signed-off-by: Suman Anna <s-anna@ti.com>
+---
+ drivers/remoteproc/pru_rproc.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c
+index c346899d5e3b..7ef176170b18 100644
+--- a/drivers/remoteproc/pru_rproc.c
++++ b/drivers/remoteproc/pru_rproc.c
+@@ -122,6 +122,7 @@ struct pru_private_data {
+  * @dbg_single_step: debug state variable to set PRU into single step mode
+  * @dbg_continuous: debug state variable to restore PRU execution mode
+  * @evt_count: number of mapped events
++ * @gpmux_save: saved value for gpmux config
+  */
+ struct pru_rproc {
+ 	int id;
+@@ -140,6 +141,7 @@ struct pru_rproc {
+ 	u32 dbg_single_step;
+ 	u32 dbg_continuous;
+ 	u8 evt_count;
++	u8 gpmux_save;
+ };
+ 
+ static inline u32 pru_control_read_reg(struct pru_rproc *pru, unsigned int reg)
+@@ -249,6 +251,7 @@ struct rproc *pru_rproc_get(struct device_node *np, int index,
+ 	const char *fw_name;
+ 	struct device *dev;
+ 	int ret;
++	u32 mux;
+ 
+ 	rproc = __pru_rproc_get(np, index);
+ 	if (IS_ERR(rproc))
+@@ -270,6 +273,22 @@ struct rproc *pru_rproc_get(struct device_node *np, int index,
+ 
+ 	mutex_unlock(&pru->lock);
+ 
++	ret = pruss_cfg_get_gpmux(pru->pruss, pru->id, &pru->gpmux_save);
++	if (ret) {
++		dev_err(dev, "failed to get cfg gpmux: %d\n", ret);
++		goto err;
++	}
++
++	ret = of_property_read_u32_index(np, "ti,pruss-gp-mux-sel", index,
++					 &mux);
++	if (!ret) {
++		ret = pruss_cfg_set_gpmux(pru->pruss, pru->id, mux);
++		if (ret) {
++			dev_err(dev, "failed to set cfg gpmux: %d\n", ret);
++			goto err;
++		}
++	}
++
+ 	ret = of_property_read_string_index(np, "firmware-name", index,
+ 					    &fw_name);
+ 	if (!ret) {
+@@ -309,6 +328,8 @@ void pru_rproc_put(struct rproc *rproc)
+ 	if (!pru->client_np)
+ 		return;
+ 
++	pruss_cfg_set_gpmux(pru->pruss, pru->id, pru->gpmux_save);
++
+ 	pru_rproc_set_firmware(rproc, NULL);
+ 
+ 	mutex_lock(&pru->lock);

board/PSG/iot2050/files/patches-5.10/0070-net-ethernet-ti-prueth-Add-IEP-driver.patch

@@ -0,0 +1,1147 @@
+From badd9f614149994f5fad336b08f136335fb334f3 Mon Sep 17 00:00:00 2001
+From: Roger Quadros <rogerq@ti.com>
+Date: Tue, 20 Apr 2021 13:17:30 +0530
+Subject: [PATCH] net: ethernet: ti: prueth: Add IEP driver
+
+Add a driver for Industrial Ethernet Peripheral (IEP) block of PRUSS to
+support timestamping of ethernet packets and thus support PTP and PPS
+for PRU ethernet ports.
+
+Signed-off-by: Roger Quadros <rogerq@ti.com>
+Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
+Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
+Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
+---
+ drivers/net/ethernet/ti/Kconfig    |    8 +
+ drivers/net/ethernet/ti/Makefile   |    2 +
+ drivers/net/ethernet/ti/icss_iep.c | 1049 ++++++++++++++++++++++++++++
+ drivers/net/ethernet/ti/icss_iep.h |   37 +
+ 4 files changed, 1096 insertions(+)
+ create mode 100644 drivers/net/ethernet/ti/icss_iep.c
+ create mode 100644 drivers/net/ethernet/ti/icss_iep.h
+
+diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig
+index abfc4c435d59..bf497da88814 100644
+--- a/drivers/net/ethernet/ti/Kconfig
++++ b/drivers/net/ethernet/ti/Kconfig
+@@ -171,4 +171,12 @@ config CPMAC
+ 	help
+ 	  TI AR7 CPMAC Ethernet support
+ 
++config TI_ICSS_IEP
++	tristate "TI PRU ICSS IEP driver"
++	depends on TI_PRUSS
++	default TI_PRUSS
++	help
++	  This enables support for the PRU-ICSS Industrial Ethernet Peripheral
++	  within a PRU-ICSS subsystem present on various TI SoCs.
++
+ endif # NET_VENDOR_TI
+diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile
+index 6e779292545d..ec94422a572f 100644
+--- a/drivers/net/ethernet/ti/Makefile
++++ b/drivers/net/ethernet/ti/Makefile
+@@ -27,3 +27,5 @@ keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o cpsw_ale.
+ obj-$(CONFIG_TI_K3_AM65_CPSW_NUSS) += ti-am65-cpsw-nuss.o
+ ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o k3-cppi-desc-pool.o am65-cpsw-qos.o
+ obj-$(CONFIG_TI_K3_AM65_CPTS) += am65-cpts.o
++
++obj-$(CONFIG_TI_ICSS_IEP) += icss_iep.o
+diff --git a/drivers/net/ethernet/ti/icss_iep.c b/drivers/net/ethernet/ti/icss_iep.c
+new file mode 100644
+index 000000000000..234972a034a9
+--- /dev/null
++++ b/drivers/net/ethernet/ti/icss_iep.c
+@@ -0,0 +1,1049 @@
++// SPDX-License-Identifier: GPL-2.0
++/* Texas Instruments ICSSG Industrial Ethernet Peripheral (IEP) Driver
++ *
++ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com
++ *
++ */
++
++#include <linux/bitops.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/timekeeping.h>
++#include <linux/interrupt.h>
++#include <linux/of_irq.h>
++
++#include "icss_iep.h"
++
++#define IEP_MAX_DEF_INC		0xf
++#define IEP_MAX_COMPEN_INC		0xfff
++#define IEP_MAX_COMPEN_COUNT	0xffffff
++
++#define IEP_GLOBAL_CFG_CNT_ENABLE	BIT(0)
++#define IEP_GLOBAL_CFG_DEFAULT_INC_MASK		GENMASK(7, 4)
++#define IEP_GLOBAL_CFG_DEFAULT_INC_SHIFT	4
++#define IEP_GLOBAL_CFG_COMPEN_INC_MASK		GENMASK(19, 8)
++#define IEP_GLOBAL_CFG_COMPEN_INC_SHIFT		8
++
++#define IEP_GLOBAL_STATUS_CNT_OVF	BIT(0)
++
++#define CMP_INDEX(sync)			((sync) + 1)
++#define IEP_CMP_CFG_SHADOW_EN		BIT(17)
++#define IEP_CMP_CFG_CMP0_RST_CNT_EN	BIT(0)
++#define IEP_CMP_CFG_CMP_EN(cmp)		(GENMASK(16, 1) & (1 << ((cmp) + 1)))
++
++#define IEP_CMP_STATUS(cmp)		(1 << (cmp))
++
++#define IEP_SYNC_CTRL_SYNC_EN		BIT(0)
++#define IEP_SYNC_CTRL_SYNC_N_EN(n)	(GENMASK(2, 1) & (BIT(1) << (n)))
++
++#define IEP_MIN_CMP	0
++#define IEP_MAX_CMP	15
++
++#define ICSS_IEP_64BIT_COUNTER_SUPPORT		BIT(0)
++#define ICSS_IEP_SLOW_COMPEN_REG_SUPPORT	BIT(1)
++#define ICSS_IEP_SHADOW_MODE_SUPPORT		BIT(2)
++
++#define LATCH_INDEX(ts_index)			((ts_index) + 6)
++#define IEP_CAP_CFG_CAPNR_1ST_EVENT_EN(n)	BIT(LATCH_INDEX(n))
++#define IEP_CAP_CFG_CAPNF_1ST_EVENT_EN(n)	BIT(LATCH_INDEX(n) + 1)
++#define IEP_CAP_CFG_CAP_ASYNC_EN(n)		BIT(LATCH_INDEX(n) + 10)
++
++enum {
++	ICSS_IEP_GLOBAL_CFG_REG,
++	ICSS_IEP_GLOBAL_STATUS_REG,
++	ICSS_IEP_COMPEN_REG,
++	ICSS_IEP_SLOW_COMPEN_REG,
++	ICSS_IEP_COUNT_REG0,
++	ICSS_IEP_COUNT_REG1,
++	ICSS_IEP_CAPTURE_CFG_REG,
++	ICSS_IEP_CAPTURE_STAT_REG,
++
++	ICSS_IEP_CAP6_RISE_REG0,
++	ICSS_IEP_CAP6_RISE_REG1,
++	ICSS_IEP_CAP6_FALL_REG0,
++	ICSS_IEP_CAP6_FALL_REG1,
++
++	ICSS_IEP_CAP7_RISE_REG0,
++	ICSS_IEP_CAP7_RISE_REG1,
++	ICSS_IEP_CAP7_FALL_REG0,
++	ICSS_IEP_CAP7_FALL_REG1,
++
++	ICSS_IEP_CMP_CFG_REG,
++	ICSS_IEP_CMP_STAT_REG,
++	ICSS_IEP_CMP0_REG0,
++	ICSS_IEP_CMP0_REG1,
++	ICSS_IEP_CMP1_REG0,
++	ICSS_IEP_CMP1_REG1,
++
++	ICSS_IEP_CMP8_REG0,
++	ICSS_IEP_CMP8_REG1,
++	ICSS_IEP_SYNC_CTRL_REG,
++	ICSS_IEP_SYNC0_STAT_REG,
++	ICSS_IEP_SYNC1_STAT_REG,
++	ICSS_IEP_SYNC_PWIDTH_REG,
++	ICSS_IEP_SYNC0_PERIOD_REG,
++	ICSS_IEP_SYNC1_DELAY_REG,
++	ICSS_IEP_SYNC_START_REG,
++	ICSS_IEP_MAX_REGS,
++};
++
++/**
++ * struct icss_iep_plat_data - Plat data to handle SoC variants
++ * @config: Regmap configuration data
++ * @reg_offs: register offsets to capture offset differences across SoCs
++ * @flags: Flags to represent IEP properties
++ */
++struct icss_iep_plat_data {
++	struct regmap_config *config;
++	u32 reg_offs[ICSS_IEP_MAX_REGS];
++	u32 flags;
++};
++
++struct icss_iep {
++	struct device *dev;
++	void __iomem *base;
++	const struct icss_iep_plat_data *plat_data;
++	struct regmap *map;
++	struct device_node *client_np;
++	unsigned long refclk_freq;
++	int clk_tick_time;	/* one refclk tick time in ns */
++	struct ptp_clock_info ptp_info;
++	struct ptp_clock *ptp_clock;
++	struct mutex ptp_clk_mutex;	/* PHC access serializer */
++	u32 def_inc;
++	s16 slow_cmp_inc;
++	u32 slow_cmp_count;
++	const struct icss_iep_clockops *ops;
++	void *clockops_data;
++	u32 cycle_time_ns;
++	u32 perout_enabled;
++	bool pps_enabled;
++	int cap_cmp_irq;
++	struct ptp_clock_time period;
++	u32 latch_enable;
++};
++
++/**
++ * icss_iep_get_count_hi() - Get the upper 32 bit IEP counter
++ * @iep: Pointer to structure representing IEP.
++ *
++ * Return: upper 32 bit IEP counter
++ */
++int icss_iep_get_count_hi(struct icss_iep *iep)
++{
++	u32 val = 0;
++
++	if (iep && (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT))
++		regmap_read(iep->map, ICSS_IEP_COUNT_REG1, &val);
++
++	return val;
++}
++EXPORT_SYMBOL_GPL(icss_iep_get_count_hi);
++
++/**
++ * icss_iep_get_count_low() - Get the lower 32 bit IEP counter
++ * @iep: Pointer to structure representing IEP.
++ *
++ * Return: lower 32 bit IEP counter
++ */
++int icss_iep_get_count_low(struct icss_iep *iep)
++{
++	u32 val = 0;
++
++	if (iep)
++		regmap_read(iep->map, ICSS_IEP_COUNT_REG0, &val);
++
++	return val;
++}
++EXPORT_SYMBOL_GPL(icss_iep_get_count_low);
++
++/**
++ * icss_iep_get_ptp_clock_idx() - Get PTP clock index using IEP driver
++ * @iep: Pointer to structure representing IEP.
++ *
++ * Return: PTP clock index, -1 if not registered
++ */
++int icss_iep_get_ptp_clock_idx(struct icss_iep *iep)
++{
++	if (!iep || !iep->ptp_clock)
++		return -1;
++	return ptp_clock_index(iep->ptp_clock);
++}
++EXPORT_SYMBOL_GPL(icss_iep_get_ptp_clock_idx);
++
++static void icss_iep_set_counter(struct icss_iep *iep, u64 ns)
++{
++	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT)
++		regmap_write(iep->map, ICSS_IEP_COUNT_REG1, upper_32_bits(ns));
++	regmap_write(iep->map, ICSS_IEP_COUNT_REG0, lower_32_bits(ns));
++}
++
++static void icss_iep_settime(struct icss_iep *iep, u64 ns)
++{
++	if (iep->ops && iep->ops->settime) {
++		iep->ops->settime(iep->clockops_data, ns);
++		return;
++	}
++
++	icss_iep_set_counter(iep, ns);
++}
++
++static u64 icss_iep_gettime(struct icss_iep *iep)
++{
++	u64 val;
++	u32 tmp;
++
++	if (iep->ops && iep->ops->gettime)
++		return iep->ops->gettime(iep->clockops_data);
++
++	regmap_read(iep->map, ICSS_IEP_COUNT_REG0, &tmp);
++	val = tmp;
++	if (iep->plat_data->flags & ICSS_IEP_64BIT_COUNTER_SUPPORT) {
++		regmap_read(iep->map, ICSS_IEP_COUNT_REG1, &tmp);
++		val |= (u64)tmp << 32;
++	}
++
++	return val;
++}
++
++static void icss_iep_enable(struct icss_iep *iep)
++{
++	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,
++			   IEP_GLOBAL_CFG_CNT_ENABLE,
++			   IEP_GLOBAL_CFG_CNT_ENABLE);
++}
++
++static void icss_iep_disable(struct icss_iep *iep)
++{
++	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,
++			   IEP_GLOBAL_CFG_CNT_ENABLE,
++			   0);
++}
++
++static void icss_iep_enable_shadow_mode(struct icss_iep *iep, u32 cycle_time_ns)
++{
++	u32 cycle_time;
++	int cmp;
++
++	/* FIXME: check why we need to decrement by def_inc */
++	cycle_time = cycle_time_ns - iep->def_inc;
++
++	icss_iep_disable(iep);
++
++	/* disable shadow mode */
++	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++			   IEP_CMP_CFG_SHADOW_EN, 0);
++
++	/* enable shadow mode */
++	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++			   IEP_CMP_CFG_SHADOW_EN, IEP_CMP_CFG_SHADOW_EN);
++
++	/* clear counters */
++	icss_iep_set_counter(iep, 0);
++
++	/* clear overflow status */
++	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_STATUS_REG,
++			   IEP_GLOBAL_STATUS_CNT_OVF,
++			   IEP_GLOBAL_STATUS_CNT_OVF);
++
++	/* clear compare status */
++	for (cmp = IEP_MIN_CMP; cmp < IEP_MAX_CMP; cmp++) {
++		regmap_update_bits(iep->map, ICSS_IEP_CMP_STAT_REG,
++				   IEP_CMP_STATUS(cmp), IEP_CMP_STATUS(cmp));
++	}
++
++	/* enable reset counter on CMP0 event */
++	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++			   IEP_CMP_CFG_CMP0_RST_CNT_EN,
++			   IEP_CMP_CFG_CMP0_RST_CNT_EN);
++	/* enable compare */
++	regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++			   IEP_CMP_CFG_CMP_EN(0),
++			   IEP_CMP_CFG_CMP_EN(0));
++
++	/* set CMP0 value to cycle time */
++	regmap_write(iep->map, ICSS_IEP_CMP0_REG0, cycle_time);
++	regmap_write(iep->map, ICSS_IEP_CMP0_REG1, cycle_time);
++
++	icss_iep_enable(iep);
++}
++
++static void icss_iep_set_default_inc(struct icss_iep *iep, u8 def_inc)
++{
++	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,
++			   IEP_GLOBAL_CFG_DEFAULT_INC_MASK,
++			   def_inc << IEP_GLOBAL_CFG_DEFAULT_INC_SHIFT);
++}
++
++static void icss_iep_set_compensation_inc(struct icss_iep *iep, u16 compen_inc)
++{
++	struct device *dev = regmap_get_device(iep->map);
++
++	if (compen_inc > IEP_MAX_COMPEN_INC) {
++		dev_err(dev, "%s: too high compensation inc %d\n",
++			__func__, compen_inc);
++		compen_inc = IEP_MAX_COMPEN_INC;
++	}
++
++	regmap_update_bits(iep->map, ICSS_IEP_GLOBAL_CFG_REG,
++			   IEP_GLOBAL_CFG_COMPEN_INC_MASK,
++			   compen_inc << IEP_GLOBAL_CFG_COMPEN_INC_SHIFT);
++}
++
++static void icss_iep_set_compensation_count(struct icss_iep *iep,
++					    u32 compen_count)
++{
++	struct device *dev = regmap_get_device(iep->map);
++
++	if (compen_count > IEP_MAX_COMPEN_COUNT) {
++		dev_err(dev, "%s: too high compensation count %d\n",
++			__func__, compen_count);
++		compen_count = IEP_MAX_COMPEN_COUNT;
++	}
++
++	regmap_write(iep->map, ICSS_IEP_COMPEN_REG, compen_count);
++}
++
++static void icss_iep_set_slow_compensation_count(struct icss_iep *iep,
++						 u32 compen_count)
++{
++	regmap_write(iep->map, ICSS_IEP_SLOW_COMPEN_REG, compen_count);
++}
++
++/* PTP PHC operations */
++static int icss_iep_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
++{
++	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);
++	u32 cyc_count;
++	u16 cmp_inc;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++
++	/* ppb is amount of frequency we want to adjust in 1GHz (billion)
++	 * e.g. 100ppb means we need to speed up clock by 100Hz
++	 * i.e. at end of 1 second (1 billion ns) clock time, we should be
++	 * counting 100 more ns.
++	 * We use IEP slow compensation to achieve continuous freq. adjustment.
++	 * There are 2 parts. Cycle time and adjustment per cycle.
++	 * Simplest case would be 1 sec Cycle time. Then adjustment
++	 * pre cycle would be (def_inc + ppb) value.
++	 * Cycle time will have to be chosen based on how worse the ppb is.
++	 * e.g. smaller the ppb, cycle time has to be large.
++	 * The minimum adjustment we can do is +-1ns per cycle so let's
++	 * reduce the cycle time to get 1ns per cycle adjustment.
++	 *	1ppb = 1sec cycle time & 1ns adjust
++	 *	1000ppb = 1/1000 cycle time & 1ns adjust per cycle
++	 */
++
++	if (iep->cycle_time_ns)
++		iep->slow_cmp_inc = iep->clk_tick_time;	/* 4ns adj per cycle */
++	else
++		iep->slow_cmp_inc = 1;	/* 1ns adjust per cycle */
++
++	if (ppb < 0) {
++		iep->slow_cmp_inc = -iep->slow_cmp_inc;
++		ppb = -ppb;
++	}
++
++	cyc_count = NSEC_PER_SEC;		/* 1s cycle time @1GHz */
++	cyc_count /= ppb;		/* cycle time per ppb */
++
++	/* slow_cmp_count is decremented every clock cycle, e.g. @250MHz */
++	if (!iep->cycle_time_ns)
++		cyc_count /= iep->clk_tick_time;
++	iep->slow_cmp_count = cyc_count;
++
++	/* iep->clk_tick_time is def_inc */
++	cmp_inc = iep->clk_tick_time + iep->slow_cmp_inc;
++	icss_iep_set_compensation_inc(iep, cmp_inc);
++	icss_iep_set_slow_compensation_count(iep, iep->slow_cmp_count);
++
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return 0;
++}
++
++static int icss_iep_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
++{
++	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);
++	s64 ns;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++	if (iep->ops && iep->ops->adjtime) {
++		iep->ops->adjtime(iep->clockops_data, delta);
++	} else {
++		ns = icss_iep_gettime(iep);
++		ns += delta;
++		icss_iep_settime(iep, ns);
++	}
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return 0;
++}
++
++static int icss_iep_ptp_gettime(struct ptp_clock_info *ptp,
++				struct timespec64 *ts)
++{
++	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);
++	u64 ns;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++	ns = icss_iep_gettime(iep);
++	*ts = ns_to_timespec64(ns);
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return 0;
++}
++
++static int icss_iep_ptp_settime(struct ptp_clock_info *ptp,
++				const struct timespec64 *ts)
++{
++	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);
++	u64 ns;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++	ns = timespec64_to_ns(ts);
++	icss_iep_settime(iep, ns);
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return 0;
++}
++
++static void icss_iep_update_to_next_boundary(struct icss_iep *iep)
++{
++	u64 ns, p_ns;
++	u32 offset;
++
++	ns = icss_iep_gettime(iep);
++	p_ns = ((u64)iep->period.sec * NSEC_PER_SEC) + iep->period.nsec;
++	/* Round up to next period boundary */
++	ns += p_ns - 1;
++	offset = do_div(ns, p_ns);
++	ns = ns * p_ns;
++	/* If it is too close to update, shift to next boundary */
++	if (p_ns - offset < 10)
++		ns += p_ns;
++
++	regmap_write(iep->map, ICSS_IEP_CMP1_REG0, lower_32_bits(ns));
++	regmap_write(iep->map, ICSS_IEP_CMP1_REG1, upper_32_bits(ns));
++}
++
++static int icss_iep_perout_enable_hw(struct icss_iep *iep,
++				     struct ptp_perout_request *req, int on)
++{
++	int ret;
++	u64 cmp;
++
++	if (iep->ops && iep->ops->perout_enable) {
++		ret = iep->ops->perout_enable(iep->clockops_data, req, on, &cmp);
++		if (ret)
++			return ret;
++
++		if (on) {
++			/* Configure CMP */
++			regmap_write(iep->map, ICSS_IEP_CMP1_REG0, lower_32_bits(cmp));
++			regmap_write(iep->map, ICSS_IEP_CMP1_REG1, upper_32_bits(cmp));
++			/* Configure SYNC */
++			regmap_write(iep->map, ICSS_IEP_SYNC_PWIDTH_REG, 1000000); /* 1ms pulse width */
++			regmap_write(iep->map, ICSS_IEP_SYNC0_PERIOD_REG, 0);
++			regmap_write(iep->map, ICSS_IEP_SYNC_START_REG, 0);
++			regmap_write(iep->map, ICSS_IEP_SYNC_CTRL_REG, 0); /* one-shot mode */
++			/* Enable CMP 1 */
++			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++					   IEP_CMP_CFG_CMP_EN(1), IEP_CMP_CFG_CMP_EN(1));
++		} else {
++			/* Disable CMP 1 */
++			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++					   IEP_CMP_CFG_CMP_EN(1), 0);
++
++			/* clear regs */
++			regmap_write(iep->map, ICSS_IEP_CMP1_REG0, 0);
++			regmap_write(iep->map, ICSS_IEP_CMP1_REG1, 0);
++		}
++	} else {
++		if (on) {
++			iep->period = req->period;
++			icss_iep_update_to_next_boundary(iep);
++			/* Enable Sync in single shot mode  */
++			regmap_write(iep->map, ICSS_IEP_SYNC_CTRL_REG,
++				     IEP_SYNC_CTRL_SYNC_N_EN(0) | IEP_SYNC_CTRL_SYNC_EN);
++			/* Enable CMP 1 */
++			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++					   IEP_CMP_CFG_CMP_EN(1), IEP_CMP_CFG_CMP_EN(1));
++		} else {
++			/* Disable CMP 1 */
++			regmap_update_bits(iep->map, ICSS_IEP_CMP_CFG_REG,
++					   IEP_CMP_CFG_CMP_EN(1), 0);
++
++			/* clear CMP regs */
++			regmap_write(iep->map, ICSS_IEP_CMP1_REG0, 0);
++			regmap_write(iep->map, ICSS_IEP_CMP1_REG1, 0);
++
++			/* Disable sync */
++			regmap_write(iep->map, ICSS_IEP_SYNC_CTRL_REG, 0);
++		}
++	}
++
++	return 0;
++}
++
++static int icss_iep_perout_enable(struct icss_iep *iep,
++				  struct ptp_perout_request *req, int on)
++{
++	int ret = 0;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++
++	if (iep->pps_enabled) {
++		ret = -EBUSY;
++		goto exit;
++	}
++
++	if (iep->perout_enabled == !!on)
++		goto exit;
++
++	ret = icss_iep_perout_enable_hw(iep, req, on);
++	if (!ret)
++		iep->perout_enabled = !!on;
++
++exit:
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return ret;
++}
++
++static irqreturn_t icss_iep_cap_cmp_handler(int irq, void *dev_id)
++{
++	struct icss_iep *iep = (struct icss_iep *)dev_id;
++	unsigned int val, index = 0, i, sts;
++	struct ptp_clock_event pevent;
++	irqreturn_t ret = IRQ_NONE;
++	u64 ns;
++
++	regmap_read(iep->map, ICSS_IEP_CMP_STAT_REG, &val);
++	if (val & BIT(CMP_INDEX(index))) {
++		regmap_write(iep->map, ICSS_IEP_CMP_STAT_REG, BIT(CMP_INDEX(index)));
++		regmap_read(iep->map, ICSS_IEP_CMP1_REG0, &val);
++		ns = val;
++		regmap_read(iep->map, ICSS_IEP_CMP1_REG1, &val);
++		ns |= (u64)val << 32;
++		icss_iep_update_to_next_boundary(iep);
++
++		pevent.pps_times.ts_real = ns_to_timespec64(ns);
++		pevent.type = PTP_CLOCK_PPSUSR;
++		pevent.index = index;
++		ptp_clock_event(iep->ptp_clock, &pevent);
++		dev_dbg(iep->dev, "IEP:pps ts: %llu\n", ns);
++		ret = IRQ_HANDLED;
++	}
++
++	regmap_read(iep->map, ICSS_IEP_CAPTURE_STAT_REG, &sts);
++	if (!sts)
++		return ret;
++
++	for (i = 0; i < iep->ptp_info.n_ext_ts; i++) {
++		if (sts & IEP_CAP_CFG_CAPNR_1ST_EVENT_EN(i * 2)) {
++			regmap_read(iep->map, ICSS_IEP_CAP6_RISE_REG0 + (i * 2), &val);
++			ns = val;
++			regmap_read(iep->map, ICSS_IEP_CAP6_RISE_REG0 + (i * 2) + 1, &val);
++			ns |= (u64)val << 32;
++			pevent.timestamp = ns;
++			pevent.type = PTP_CLOCK_EXTTS;
++			pevent.index = i;
++			ptp_clock_event(iep->ptp_clock, &pevent);
++			dev_dbg(iep->dev, "IEP:extts index=%d ts: %llu\n", i, ns);
++			ret = IRQ_HANDLED;
++		}
++	}
++
++	return ret;
++}
++
++static int icss_iep_pps_enable(struct icss_iep *iep, int on)
++{
++	int ret = 0;
++	struct timespec64 ts;
++	struct ptp_clock_request rq;
++	u64 ns;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++
++	if (iep->perout_enabled) {
++		ret = -EBUSY;
++		goto exit;
++	}
++
++	if (iep->pps_enabled == !!on)
++		goto exit;
++
++	rq.perout.index = 0;
++	if (on) {
++		ns = icss_iep_gettime(iep);
++		ts = ns_to_timespec64(ns);
++		rq.perout.period.sec = 1;
++		rq.perout.period.nsec = 0;
++		rq.perout.start.sec = ts.tv_sec + 2;
++		rq.perout.start.nsec = 0;
++		ret = icss_iep_perout_enable_hw(iep, &rq.perout, on);
++	} else {
++		ret = icss_iep_perout_enable_hw(iep, &rq.perout, on);
++	}
++
++	if (!ret)
++		iep->pps_enabled = !!on;
++
++exit:
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return ret;
++}
++
++static int icss_iep_extts_enable(struct icss_iep *iep, u32 index, int on)
++{
++	u32 val, cap, ret = 0;
++
++	mutex_lock(&iep->ptp_clk_mutex);
++
++	if (iep->ops && iep->ops->extts_enable) {
++		ret = iep->ops->extts_enable(iep->clockops_data, index, on);
++		goto exit;
++	}
++
++	if (!!(iep->latch_enable & BIT(index)) == !!on)
++		goto exit;
++
++	regmap_read(iep->map, ICSS_IEP_CAPTURE_CFG_REG, &val);
++	cap = IEP_CAP_CFG_CAP_ASYNC_EN(index) | IEP_CAP_CFG_CAPNR_1ST_EVENT_EN(index);
++	if (on) {
++		val |= cap;
++		iep->latch_enable |= BIT(index);
++	} else {
++		val &= ~cap;
++		iep->latch_enable &= ~BIT(index);
++	}
++	regmap_write(iep->map, ICSS_IEP_CAPTURE_CFG_REG, val);
++
++exit:
++	mutex_unlock(&iep->ptp_clk_mutex);
++
++	return ret;
++}
++
++static int icss_iep_ptp_enable(struct ptp_clock_info *ptp,
++			       struct ptp_clock_request *rq, int on)
++{
++	struct icss_iep *iep = container_of(ptp, struct icss_iep, ptp_info);
++
++	switch (rq->type) {
++	case PTP_CLK_REQ_PEROUT:
++		return icss_iep_perout_enable(iep, &rq->perout, on);
++	case PTP_CLK_REQ_PPS:
++		return icss_iep_pps_enable(iep, on);
++	case PTP_CLK_REQ_EXTTS:
++		return icss_iep_extts_enable(iep, rq->extts.index, on);
++	default:
++		break;
++	}
++
++	return -EOPNOTSUPP;
++}
++
++static struct ptp_clock_info icss_iep_ptp_info = {
++	.owner		= THIS_MODULE,
++	.name		= "ICSS IEP timer",
++	.max_adj	= 10000000,
++	.adjfreq	= icss_iep_ptp_adjfreq,
++	.adjtime	= icss_iep_ptp_adjtime,
++	.gettime64	= icss_iep_ptp_gettime,
++	.settime64	= icss_iep_ptp_settime,
++	.enable		= icss_iep_ptp_enable,
++};
++
++struct icss_iep *icss_iep_get(struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct device_node *iep_np;
++	struct icss_iep *iep;
++	int ret;
++
++	iep_np = of_parse_phandle(np, "iep", 0);
++	if (!iep_np || !of_device_is_available(iep_np))
++		return ERR_PTR(-ENODEV);
++
++	pdev = of_find_device_by_node(iep_np);
++	of_node_put(iep_np);
++
++	if (!pdev)
++		/* probably IEP not yet probed */
++		return ERR_PTR(-EPROBE_DEFER);
++
++	iep = platform_get_drvdata(pdev);
++	if (!iep)
++		return ERR_PTR(-EPROBE_DEFER);
++
++	device_lock(iep->dev);
++	if (iep->client_np) {
++		device_unlock(iep->dev);
++		dev_err(iep->dev, "IEP is already acquired by %s",
++			iep->client_np->name);
++		return ERR_PTR(-EBUSY);
++	}
++	iep->client_np = np;
++	device_unlock(iep->dev);
++	get_device(iep->dev);
++
++	iep->cap_cmp_irq = of_irq_get_byname(np, "iep_cap_cmp");
++	if (iep->cap_cmp_irq < 0) {
++		iep->cap_cmp_irq = 0;
++	} else {
++		ret = request_irq(iep->cap_cmp_irq, icss_iep_cap_cmp_handler, IRQF_TRIGGER_HIGH,
++				  "iep_cap_cmp", iep);
++		if (ret) {
++			dev_err(iep->dev, "Request irq failed for cap_cmp %d\n", ret);
++			goto put_iep_device;
++		}
++	}
++
++	iep->ptp_info = icss_iep_ptp_info;
++
++	if (iep->cap_cmp_irq || (iep->ops && iep->ops->perout_enable)) {
++		iep->ptp_info.n_per_out = 1;
++		iep->ptp_info.pps = 1;
++	}
++
++	if (iep->cap_cmp_irq || (iep->ops && iep->ops->extts_enable))
++		iep->ptp_info.n_ext_ts = 2;
++
++	return iep;
++
++put_iep_device:
++	put_device(iep->dev);
++
++	return ERR_PTR(ret);
++}
++EXPORT_SYMBOL_GPL(icss_iep_get);
++
++void icss_iep_put(struct icss_iep *iep)
++{
++	device_lock(iep->dev);
++	iep->client_np = NULL;
++	device_unlock(iep->dev);
++	put_device(iep->dev);
++	if (iep->cap_cmp_irq)
++		free_irq(iep->cap_cmp_irq, iep);
++}
++EXPORT_SYMBOL_GPL(icss_iep_put);
++
++int icss_iep_init(struct icss_iep *iep, const struct icss_iep_clockops *clkops,
++		  void *clockops_data, u32 cycle_time_ns)
++{
++	u32 def_inc;
++	int ret = 0;
++
++	def_inc = NSEC_PER_SEC / iep->refclk_freq;	/* ns per clock tick */
++	if (def_inc > IEP_MAX_DEF_INC)
++		/* iep_core_clk too slow to be supported */
++		return -EINVAL;
++
++	iep->def_inc = def_inc;
++	iep->ops = clkops;
++	iep->clockops_data = clockops_data;
++	icss_iep_set_default_inc(iep, def_inc);
++	icss_iep_set_compensation_inc(iep, def_inc);
++	icss_iep_set_compensation_count(iep, 0);
++	regmap_write(iep->map, ICSS_IEP_SYNC_PWIDTH_REG, iep->refclk_freq / 10); /* 100 ms pulse */
++	regmap_write(iep->map, ICSS_IEP_SYNC0_PERIOD_REG, 0);
++	if (iep->plat_data->flags & ICSS_IEP_SLOW_COMPEN_REG_SUPPORT)
++		icss_iep_set_slow_compensation_count(iep, 0);
++	if (cycle_time_ns)
++		icss_iep_enable_shadow_mode(iep, cycle_time_ns);
++	else
++		icss_iep_enable(iep);
++
++	iep->cycle_time_ns = cycle_time_ns;
++	icss_iep_set_counter(iep, 0);
++
++	iep->clk_tick_time = def_inc;
++
++	iep->ptp_clock = ptp_clock_register(&iep->ptp_info, iep->dev);
++	if (IS_ERR(iep->ptp_clock)) {
++		ret = PTR_ERR(iep->ptp_clock);
++		iep->ptp_clock = NULL;
++		dev_err(iep->dev, "Failed to register ptp clk %d\n", ret);
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(icss_iep_init);
++
++int icss_iep_exit(struct icss_iep *iep)
++{
++	if (iep->ptp_clock) {
++		ptp_clock_unregister(iep->ptp_clock);
++		iep->ptp_clock = NULL;
++	}
++	icss_iep_disable(iep);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(icss_iep_exit);
++
++static const struct of_device_id icss_iep_of_match[];
++
++static int icss_iep_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct icss_iep *iep;
++	struct resource *res;
++	struct clk *iep_clk;
++
++	iep = devm_kzalloc(dev, sizeof(*iep), GFP_KERNEL);
++	if (!iep)
++		return -ENOMEM;
++
++	iep->dev = dev;
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	iep->base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(iep->base))
++		return -ENODEV;
++
++	iep_clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(iep_clk))
++		return PTR_ERR(iep_clk);
++
++	iep->refclk_freq = clk_get_rate(iep_clk);
++
++	iep->plat_data = of_device_get_match_data(dev);
++	if (!iep->plat_data)
++		return -EINVAL;
++
++	iep->map = devm_regmap_init(dev, NULL, iep, iep->plat_data->config);
++	if (IS_ERR(iep->map)) {
++		dev_err(dev, "Failed to create regmap for IEP %ld\n",
++			PTR_ERR(iep->map));
++		return PTR_ERR(iep->map);
++	}
++
++	mutex_init(&iep->ptp_clk_mutex);
++	dev_set_drvdata(dev, iep);
++	icss_iep_disable(iep);
++
++	return 0;
++}
++
++static bool am654_icss_iep_valid_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case ICSS_IEP_GLOBAL_CFG_REG ... ICSS_IEP_SYNC_START_REG:
++		return true;
++	default:
++		return false;
++	}
++
++	return false;
++}
++
++static int icss_iep_regmap_write(void *context, unsigned int reg,
++				 unsigned int val)
++{
++	struct icss_iep *iep = context;
++
++	writel(val, iep->base + iep->plat_data->reg_offs[reg]);
++
++	return 0;
++}
++
++static int icss_iep_regmap_read(void *context, unsigned int reg,
++				unsigned int *val)
++{
++	struct icss_iep *iep = context;
++
++	*val = readl(iep->base + iep->plat_data->reg_offs[reg]);
++
++	return 0;
++}
++
++static struct regmap_config am654_icss_iep_regmap_config = {
++	.name = "icss iep",
++	.reg_stride = 1,
++	.reg_write = icss_iep_regmap_write,
++	.reg_read = icss_iep_regmap_read,
++	.writeable_reg = am654_icss_iep_valid_reg,
++	.readable_reg = am654_icss_iep_valid_reg,
++};
++
++static const struct icss_iep_plat_data am654_icss_iep_plat_data = {
++	.flags = ICSS_IEP_64BIT_COUNTER_SUPPORT |
++		 ICSS_IEP_SLOW_COMPEN_REG_SUPPORT |
++		 ICSS_IEP_SHADOW_MODE_SUPPORT,
++	.reg_offs = {
++		[ICSS_IEP_GLOBAL_CFG_REG] = 0x00,
++		[ICSS_IEP_COMPEN_REG] = 0x08,
++		[ICSS_IEP_SLOW_COMPEN_REG] = 0x0C,
++		[ICSS_IEP_COUNT_REG0] = 0x10,
++		[ICSS_IEP_COUNT_REG1] = 0x14,
++		[ICSS_IEP_CAPTURE_CFG_REG] = 0x18,
++		[ICSS_IEP_CAPTURE_STAT_REG] = 0x1c,
++
++		[ICSS_IEP_CAP6_RISE_REG0] = 0x50,
++		[ICSS_IEP_CAP6_RISE_REG1] = 0x54,
++		[ICSS_IEP_CAP6_FALL_REG0] = 0x58,
++		[ICSS_IEP_CAP6_FALL_REG1] = 0x5c,
++
++		[ICSS_IEP_CAP7_RISE_REG0] = 0x60,
++		[ICSS_IEP_CAP7_RISE_REG1] = 0x64,
++		[ICSS_IEP_CAP7_FALL_REG0] = 0x68,
++		[ICSS_IEP_CAP7_FALL_REG1] = 0x6c,
++
++		[ICSS_IEP_CMP_CFG_REG] = 0x70,
++		[ICSS_IEP_CMP_STAT_REG] = 0x74,
++		[ICSS_IEP_CMP0_REG0] = 0x78,
++		[ICSS_IEP_CMP0_REG1] = 0x7c,
++		[ICSS_IEP_CMP1_REG0] = 0x80,
++		[ICSS_IEP_CMP1_REG1] = 0x84,
++
++		[ICSS_IEP_CMP8_REG0] = 0xc0,
++		[ICSS_IEP_CMP8_REG1] = 0xc4,
++		[ICSS_IEP_SYNC_CTRL_REG] = 0x180,
++		[ICSS_IEP_SYNC0_STAT_REG] = 0x188,
++		[ICSS_IEP_SYNC1_STAT_REG] = 0x18c,
++		[ICSS_IEP_SYNC_PWIDTH_REG] = 0x190,
++		[ICSS_IEP_SYNC0_PERIOD_REG] = 0x194,
++		[ICSS_IEP_SYNC1_DELAY_REG] = 0x198,
++		[ICSS_IEP_SYNC_START_REG] = 0x19c,
++	},
++	.config = &am654_icss_iep_regmap_config,
++};
++
++static const struct icss_iep_plat_data am57xx_icss_iep_plat_data = {
++	.flags = ICSS_IEP_64BIT_COUNTER_SUPPORT |
++		 ICSS_IEP_SLOW_COMPEN_REG_SUPPORT,
++	.reg_offs = {
++		[ICSS_IEP_GLOBAL_CFG_REG] = 0x00,
++		[ICSS_IEP_COMPEN_REG] = 0x08,
++		[ICSS_IEP_SLOW_COMPEN_REG] = 0x0C,
++		[ICSS_IEP_COUNT_REG0] = 0x10,
++		[ICSS_IEP_COUNT_REG1] = 0x14,
++		[ICSS_IEP_CAPTURE_CFG_REG] = 0x18,
++		[ICSS_IEP_CAPTURE_STAT_REG] = 0x1c,
++
++		[ICSS_IEP_CAP6_RISE_REG0] = 0x50,
++		[ICSS_IEP_CAP6_RISE_REG1] = 0x54,
++		[ICSS_IEP_CAP6_FALL_REG0] = 0x58,
++		[ICSS_IEP_CAP6_FALL_REG1] = 0x5c,
++
++		[ICSS_IEP_CAP7_RISE_REG0] = 0x60,
++		[ICSS_IEP_CAP7_RISE_REG1] = 0x64,
++		[ICSS_IEP_CAP7_FALL_REG0] = 0x68,
++		[ICSS_IEP_CAP7_FALL_REG1] = 0x6c,
++
++		[ICSS_IEP_CMP_CFG_REG] = 0x70,
++		[ICSS_IEP_CMP_STAT_REG] = 0x74,
++		[ICSS_IEP_CMP0_REG0] = 0x78,
++		[ICSS_IEP_CMP0_REG1] = 0x7c,
++		[ICSS_IEP_CMP1_REG0] = 0x80,
++		[ICSS_IEP_CMP1_REG1] = 0x84,
++
++		[ICSS_IEP_CMP8_REG0] = 0xc0,
++		[ICSS_IEP_CMP8_REG1] = 0xc4,
++		[ICSS_IEP_SYNC_CTRL_REG] = 0x180,
++		[ICSS_IEP_SYNC0_STAT_REG] = 0x188,
++		[ICSS_IEP_SYNC1_STAT_REG] = 0x18c,
++		[ICSS_IEP_SYNC_PWIDTH_REG] = 0x190,
++		[ICSS_IEP_SYNC0_PERIOD_REG] = 0x194,
++		[ICSS_IEP_SYNC1_DELAY_REG] = 0x198,
++		[ICSS_IEP_SYNC_START_REG] = 0x19c,
++	},
++	.config = &am654_icss_iep_regmap_config,
++};
++
++static bool am335x_icss_iep_valid_reg(struct device *dev, unsigned int reg)
++{
++	switch (reg) {
++	case ICSS_IEP_GLOBAL_CFG_REG ... ICSS_IEP_CAPTURE_STAT_REG:
++	case ICSS_IEP_CAP6_RISE_REG0:
++	case ICSS_IEP_CAP6_FALL_REG0:
++	case ICSS_IEP_CMP_CFG_REG ... ICSS_IEP_CMP0_REG0:
++	case ICSS_IEP_CMP8_REG0 ... ICSS_IEP_SYNC_START_REG:
++		return true;
++	default:
++		return false;
++	}
++
++	return false;
++}
++
++static struct regmap_config am335x_icss_iep_regmap_config = {
++	.name = "icss iep",
++	.reg_stride = 1,
++	.reg_write = icss_iep_regmap_write,
++	.reg_read = icss_iep_regmap_read,
++	.writeable_reg = am335x_icss_iep_valid_reg,
++	.readable_reg = am335x_icss_iep_valid_reg,
++};
++
++static const struct icss_iep_plat_data am335x_icss_iep_plat_data = {
++	.flags = 0,
++	.reg_offs = {
++		[ICSS_IEP_GLOBAL_CFG_REG] = 0x00,
++		[ICSS_IEP_COMPEN_REG] = 0x08,
++		[ICSS_IEP_COUNT_REG0] = 0x0C,
++		[ICSS_IEP_CAPTURE_CFG_REG] = 0x10,
++		[ICSS_IEP_CAPTURE_STAT_REG] = 0x14,
++
++		[ICSS_IEP_CAP6_RISE_REG0] = 0x30,
++		[ICSS_IEP_CAP6_FALL_REG0] = 0x34,
++
++		[ICSS_IEP_CAP7_RISE_REG0] = 0x38,
++		[ICSS_IEP_CAP7_FALL_REG0] = 0x3C,
++
++		[ICSS_IEP_CMP_CFG_REG] = 0x40,
++		[ICSS_IEP_CMP_STAT_REG] = 0x44,
++		[ICSS_IEP_CMP0_REG0] = 0x48,
++
++		[ICSS_IEP_CMP8_REG0] = 0x88,
++		[ICSS_IEP_SYNC_CTRL_REG] = 0x100,
++		[ICSS_IEP_SYNC0_STAT_REG] = 0x108,
++		[ICSS_IEP_SYNC1_STAT_REG] = 0x10C,
++		[ICSS_IEP_SYNC_PWIDTH_REG] = 0x110,
++		[ICSS_IEP_SYNC0_PERIOD_REG] = 0x114,
++		[ICSS_IEP_SYNC1_DELAY_REG] = 0x118,
++		[ICSS_IEP_SYNC_START_REG] = 0x11C,
++	},
++	.config = &am335x_icss_iep_regmap_config,
++};
++
++static const struct of_device_id icss_iep_of_match[] = {
++	{
++		.compatible = "ti,am654-icss-iep",
++		.data = &am654_icss_iep_plat_data,
++	},
++	{
++		.compatible = "ti,am5728-icss-iep",
++		.data = &am57xx_icss_iep_plat_data,
++	},
++	{
++		.compatible = "ti,am3356-icss-iep",
++		.data = &am335x_icss_iep_plat_data,
++	},
++	{},
++};
++MODULE_DEVICE_TABLE(of, icss_iep_of_match);
++
++static struct platform_driver icss_iep_driver = {
++	.driver = {
++		.name = "icss-iep",
++		.of_match_table = of_match_ptr(icss_iep_of_match),
++	},
++	.probe = icss_iep_probe,
++};
++module_platform_driver(icss_iep_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("TI ICSS IEP driver");
++MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
+diff --git a/drivers/net/ethernet/ti/icss_iep.h b/drivers/net/ethernet/ti/icss_iep.h
+new file mode 100644
+index 000000000000..a41e18df666e
+--- /dev/null
++++ b/drivers/net/ethernet/ti/icss_iep.h
+@@ -0,0 +1,37 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/* Texas Instruments ICSSG Industrial Ethernet Peripheral (IEP) Driver
++ *
++ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
++ *
++ */
++
++#ifndef __NET_TI_ICSS_IEP_H
++#define __NET_TI_ICSS_IEP_H
++
++#include <linux/mutex.h>
++#include <linux/ptp_clock_kernel.h>
++#include <linux/regmap.h>
++
++struct icss_iep;
++
++/* Firmware specific clock operations */
++struct icss_iep_clockops {
++	void (*settime)(void *clockops_data, u64 ns);
++	void (*adjtime)(void *clockops_data, s64 delta);
++	u64 (*gettime)(void *clockops_data);
++	int (*perout_enable)(void *clockops_data,
++			     struct ptp_perout_request *req, int on,
++			     u64 *cmp);
++	int (*extts_enable)(void *clockops_data, u32 index, int on);
++};
++
++struct icss_iep *icss_iep_get(struct device_node *np);
++void icss_iep_put(struct icss_iep *iep);
++int icss_iep_init(struct icss_iep *iep, const struct icss_iep_clockops *clkops,
++		  void *clockops_data, u32 cycle_time_ns);
++int icss_iep_exit(struct icss_iep *iep);
++int icss_iep_get_count_low(struct icss_iep *iep);
++int icss_iep_get_count_hi(struct icss_iep *iep);
++int icss_iep_get_ptp_clock_idx(struct icss_iep *iep);
++
++#endif /* __NET_TI_ICSS_IEP_H */